Plating for thermal management

Patent metadata

Field	Value
Publication number	US-12068221-B2
Application number	US-202016985103-A
Country	US
Kind code	B2
Filing date	Aug 4, 2020
Priority date	Nov 16, 2018
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

Described examples include a process that includes forming a diffusion barrier layer on a backside of a semiconductor wafer. The process also includes forming a seed copper layer on the diffusion barrier layer. The process also includes forming a copper layer on the seed copper layer. The process also includes immersion plating a silver layer on the copper layer.

First claim

What is claimed is:

1. A process for making a semiconductor device, comprising:
forming a first diffusion barrier layer on an active side of a semiconductor wafer;
forming a second diffusion barrier layer on a backside of the semiconductor wafer;
forming a first seed copper layer on the first diffusion barrier layer;
forming a second seed copper layer on the second diffusion barrier layer;
forming a first copper layer on the first seed copper layer;
forming a second copper layer on the second seed copper layer; and
immersion plating a silver layer on the second copper layer.

2. The process of claim 1 in which the second diffusion barrier layer is a titanium-tungsten layer.

3. The process of claim 1 in which the forming of the second seed copper layer includes sputtering the second seed copper layer.

4. The process of claim 1 in which the forming of the second copper layer includes plating the second copper layer.

5. The process of claim 1 further including:
patterning the second copper layer, the second seed copper layer and the second diffusion barrier layer;
dicing the semiconductor wafer to form a semiconductor die;
attaching the semiconductor die to a substrate; and
molding portions of the semiconductor die and the substrate with a mold compound.

6. The process of claim 1 in which the immersion plated silver layer includes an organic preservative.

7. A process for making a semiconductor device, comprising:
thinning a backside of a semiconductor wafer, the backside opposite an active side of the semiconductor wafer;
depositing a titanium-tungsten (TiW) layer on the backside;
forming a copper seed layer on the TiW layer;
forming photolithographic pattern over an area between dies on the semiconductor wafer;
removing some of the photolithographic pattern exposing surfaces of the copper seed layer;
forming a copper layer on exposed surfaces of the copper seed layer; and
forming a silver layer on the copper layer using immersion plating.

8. The process of claim 7 in which the titanium-tungsten (TiW) layer is deposited on the backside using sputtering, physical vapor deposition (PVD), or chemical vapor deposition.

9. The process of claim 7 in which the copper layer is deposited on the backside using sputtering, physical vapor deposition (PVD), or chemical vapor deposition.

10. The process of claim 7 in which the silver layer is formed using immersion plating.

11. A process for making a semiconductor device, comprising:
thinning a backside of a semiconductor wafer, the backside opposite an active side of the semiconductor wafer;
depositing a titanium-tungsten (TiW) layer on both the active side and the backside of the semiconductor wafer;
forming a seed copper layer on the TiW layer;
forming photoresist layers over an area between dies and on the backside of the semiconductor wafer;
patterning the photoresist layers to expose surfaces of the seed copper layer;
forming a copper layer on exposed surfaces of the seed copper layer;
removing the photoresist layer;
etching the seed copper layer and the TiW layer using the copper layer as a mask; and
forming a silver layer on the copper layer at the backside of the wafer using immersion plating.

Assignees

• Texas Instruments Inc

Inventors

• Dadvand Nazila
• Manack Christopher Daniel
• Pavone Salvatore Frank

Classifications

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P14/46

  using a liquid · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10W20/043

  for electroplating · CPC title