Semiconductor devices and processing methods

Patent metadata

Field	Value
Publication number	US-10103123-B2
Application number	US-201715455158-A
Country	US
Kind code	B2
Filing date	Mar 10, 2017
Priority date	Oct 22, 2012
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

First claim

What is claimed is:

1. A method for processing a semiconductor device, comprising:
forming a final metal layer having a top side and at least one sidewall;
forming, by an atomic layer deposition process, a passivation layer over at least part of at least one the top side of the final metal layer so that the passivation layer completely covers the top side of the final metal layer;
forming a second passivation layer to at least partially surrounding the passivation layer, wherein the second passivation layer completely covers a top side of the passivation layer;
forming a first hole through the second passivation layer so that a portion of the top side of the passivation layer is exposed;
forming an interconnect structure through or in the first hole;
electrically connecting the interconnect structure to the final metal layer, wherein electrically connecting the interconnect structure to the final metal layer further comprises,
bonding the interconnect structure to the final metal layer so that that the bonding process breaks through the passivation layer so that the interconnect structure is electrically connected to the final metal layer,

wherein the interconnect comprises an electrically conductive wire and a wire bond structure, the wire bond structure physically contacting a top side of the final metal layer.

2. The method of claim 1 , further comprising:
forming the passivation layer over at least one sidewall of the final metal layer.

3. The method of claim 1 , wherein the passivation layer is conformally formed over the top side and the at least one sidewall of the final metal layer.

4. The method of claim 1 ,
wherein the passivation layer comprises a metal oxide.

5. The method of claim 4 ,
wherein the metal oxide is an oxide, which is different from a native oxide of the final metal layer.

6. The method of claim 1 ,
wherein the passivation layer comprises aluminum oxide.

7. The method of claim 1 ,
wherein the atomic layer deposition process comprises an aluminum precursor comprising trimethylaluminum.

8. The method of claim 1 ,
wherein the atomic layer deposition process comprises at least one oxidizing precursor from the following group of oxidizing precursors, the group of oxidizing precursors consisting of: water, alcohol, isopropanol, ethanol and methanol.

9. The method of claim 1 ,
wherein the final metal layer comprises at least one metal from the following group of metals, the group of metals consisting of: copper, silver, palladium, silver, tungsten, aluminum and tin.

10. The method of claim 1 ,
wherein the second passivation layer comprises at least one material from the following group of materials, the group of materials consisting of: polyimide, epoxy, polymer, silicon dioxide, silicon nitride, silicon oxinitride.

11. The method of claim 1 , further comprising:
wherein the bonding process breaks through the passivation layer so as to form a second hole through the passivation layer, wherein a third hole comprises the first and second holes.

12. The method of claim 1 , wherein a thickness of the passivation measured from the top side of the final metal layer is in a range of 5 nm to 10 nm.

13. A method for forming a metallization structure arrangement, comprising
providing a semiconductor chip;
forming a metal contact pad directly on a top or bottom surface of the semiconductor chip, wherein the metal contact pad comprises a plurality of layers including a final metal layer and wherein, the final metal layer comprising copper and is a layer of the contact pad furthest from the semiconductor chip;
forming an aluminum oxide layer directly on the metal contact pad so that the aluminum oxide layer conformally covers at least an entire top surface of the metal contact pad and at least a portion of one or more sidewalls of the final metal layer; and
forming a passivation layer that at least partially surrounds the aluminum oxide layer, wherein the passivation layer completely covers a top side of the aluminum oxide layer;
forming a first hole through the passivation layer so that a portion of the top side of the aluminum oxide layer is exposed;
forming an interconnect structure through or in the first hole; and
electrically connecting the interconnect structure to the final metal layer, wherein electrically connecting the interconnect structure to the final metal layer further comprises,
bonding the interconnect structure to the final metal layer so that that the bonding process breaks through the aluminum oxide layer so that the interconnect structure is electrically connected to the final metal layer,

wherein the interconnect comprises an electrically conductive wire and a wire bond structure, the wire bond structure physically contacting a top side of the final metal layer.

14. The method of claim 1 , further comprising:
wherein the bonding process breaks through the aluminum oxide layer so as to form a second hole through the aluminum oxide layer, wherein a third hole comprises the first and second holes.

15. The method of claim 1 , further comprising:
wherein the wire bond structure is a ball bond or a wedge bond.

Assignees

• Infineon Technologies Ag

Inventors

• Rogalli Michael
• Lehnert Wolfgang

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title