Method for manufacturing semiconductor structure

Patent metadata

Field	Value
Publication number	US-12068160-B2
Application number	US-202117468909-A
Country	US
Kind code	B2
Filing date	Sep 8, 2021
Priority date	Feb 23, 2021
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A method for manufacturing a semiconductor structure, comprising: forming a first mask layer, a first buffer layer, a second mask layer and a second buffer layer sequentially stacked from bottom to top; patterning the second buffer layer and the second mask layer; forming a first mask pattern on a side wall of a first pattern, the first mask pattern extending in a first direction; removing the second buffer layer and the second mask layer; forming a third mask layer, a third buffer layer, a fourth mask layer and a fourth buffer layer sequentially stacked form bottom to top; patterning the fourth buffer layer and the fourth mask layer; forming a second mask pattern on a side wall of a second pattern, the second mask pattern extending in a second direction; removing the fourth buffer layer and the fourth mask layer.

First claim

The invention claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
forming a first mask layer, a first buffer layer, a second mask layer and a second buffer layer sequentially stacked from bottom to top, wherein an etching selectivity of the second buffer layer to the first buffer layer is greater than 1;
patterning the second buffer layer and the second mask layer to form a first pattern;
forming a first mask pattern on a side wall of the first pattern, the first mask pattern extending in a first direction;
removing the second buffer layer and the second mask layer;
forming a third mask layer, a third buffer layer, a fourth mask layer and a fourth buffer layer sequentially stacked from bottom to top, wherein the third mask layer covers the first buffer layer and fills up gaps in the first mask pattern, an upper surface of the third mask layer is flush with an upper surface of the first mask pattern, and an etching selectivity of the fourth buffer layer to the third buffer layer is greater than 1;
patterning the fourth buffer layer and the fourth mask layer to form a second pattern;
forming a second mask pattern on a side wall of the second pattern, the second mask pattern extending in a second direction, and the second direction being obliquely crossed with the first direction; and
removing the fourth buffer layer and the fourth mask layer;
wherein before the first pattern is formed, the method further comprises: forming a fifth buffer layer on an upper surface of the second buffer layer, wherein a material of the fifth buffer layer is the same as that of the first buffer layer;
wherein patterning the second buffer layer and the second mask layer to form the first pattern comprises:
patterning the fifth buffer layer, wherein the first pattern is defined by a patterned fifth buffer layer;
patterning the second buffer layer based on the patterned fifth buffer layer to forming a patterned second buffer layer;
removing the patterned fifth buffer layer; and
patterning the second mask layer based on the patterned second buffer layer to form the first pattern.

2. The method of claim 1 , wherein before the second pattern is formed, the method further comprises: forming a sixth buffer layer on an upper surface of the fourth buffer layer, wherein a material of the sixth buffer layer is the same as that of the third buffer layer;
wherein patterning the fourth buffer layer and the fourth mask layer to form the second pattern comprises:
patterning the sixth buffer layer, wherein the second pattern is defined by a patterned sixth buffer layer;
patterning the fourth buffer layer based on the patterned sixth buffer layer to form a patterned fourth buffer layer;
removing the patterned sixth buffer layer; and
patterning the fourth mask layer based on the patterned fourth buffer layer to form the second pattern.

3. The method of claim 2 , wherein each of the first mask layer, the second mask layer, the third mask layer and the fourth mask layer comprises a Spin-on Hardmask, and each of the first buffer layer, the third buffer layer and the sixth buffer layer comprises a silicon oxynitride layer;
each of the second buffer layer and the fourth buffer layer comprises a silicon nitride layer, and each of the first mask pattern and the second mask pattern comprises an oxide pattern; or each of the second buffer layer and the fourth buffer layer comprises an oxide layer, and each of the first mask pattern and the second mask pattern comprises a silicon nitride pattern.

4. The method of claim 1 , wherein each of the first mask layer, the second mask layer, the third mask layer and the fourth mask layer comprises a Spin-on Hardmask, and each of the first buffer layer, the third buffer layer and the fifth buffer layer comprises a silicon oxynitride layer;
each of the second buffer layer and the fourth buffer layer comprises a silicon nitride layer, and each of the first mask pattern and the second mask pattern comprises an oxide pattern; or each of the second buffer layer and the fourth buffer layer comprises an oxide layer, and each of the first mask pattern and the second mask pattern comprises a silicon nitride pattern.

5. The method of claim 4 , wherein the Spin-on Hardmask comprises an amorphous carbon layer or an amorphous silicon layer, the oxide pattern comprises a silicon oxide pattern formed through an atomic layer deposition (ALD) process, and the silicon nitride pattern comprises a silicon nitride pattern formed through the ALD process.

6. The method of claim 1 , wherein an included angle between the first direction and the second direction ranges from 55 degrees to 65 degrees.

7. The method of claim 1 , wherein before forming the first mask layer, the first buffer layer, the second mask layer and the second buffer layer sequentially stacked from bottom to top, the method further comprises:
forming a target mask layer, the target mask layer being positioned below the first mask layer;
after removing the fourth buffer layer and the fourth mask layer, the method further comprises:
removing an exposed portion of the third buffer layer and an exposed portion of the third mask layer based on the second mask pattern;
patterning the first mask layer and the first buffer layer based on the first mask pattern and the second mask pattern to form a patterned first mask layer and a patterned first buffer layer;
removing the first mask pattern, the second mask pattern, a remaining portion of the third buffer layer and a remaining portion of the third mask layer; and

patterning the target mask layer based on the patterned first buffer layer and the patterned first mask layer to obtain a patterned mask layer.

8. The method of claim 7 , wherein after the patterned mask layer is formed, the method further comprises:
removing the patterned first buffer layer and the patterned first mask layer.

9. The method of claim 7 , wherein forming the target mask layer comprises:
forming a first target mask layer; and
forming a second target mask layer on an upper surface of the first target mask layer, the first mask layer being positioned on an upper surface of the second target mask layer.

10. The method of claim 9 , wherein patterning the target mask layer based on the patterned first buffer layer and the patterned first mask layer to obtain the patterned mask layer comprises:
patterning the second target mask layer based on the patterned first buffer layer and the patterned first mask layer to obtain a second patterned target mask layer;
removing the patterned first buffer layer and the patterned first mask layer;
patterning the first target mask layer based on the second patterned target mask layer to obtain a first patterned target mask layer; and
removing the second patterned target mask layer.

11. The method of claim 10 , wherein a plurality of oval openings arranged in an array are formed in the second patterned target mask layer, a width of each of the plurality of oval openings being the same in a same direction, and a plurality of circular openings arranged in an array are formed in the first patterned target mask layer, a diameter of each of the plurality of circular openings being the same.

12. The method of claim 9 , wherein the second target mask layer comprises an oxide layer, and the first target mask layer comprises a polysilicon layer.

13. The method of claim 12 , wherein the second target mask layer comprises a silicon oxide layer formed by tetraethyl orthosilicate.

14. The method of claim 7 , wherein before forming the target mask layer, the method further comprises:
forming a stack

Assignees

• Changxin Memory Tech Inc

Inventors

• Cao Xinman
• Liu Zhongming
• Bai Shijie

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10D1/692

  Electrodes · CPC title

• H10D1/716

  having vertical extensions · CPC title