Self-aligned double patterning method

Patent metadata

Field	Value
Publication number	US-10312088-B1
Application number	US-201815900764-A
Country	US
Kind code	B1
Filing date	Feb 20, 2018
Priority date	Jan 9, 2018
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A self-aligned double patterning method includes the steps of forming line structures spaced apart from each other in a first direction on a mask layer, forming dielectric layer on the line structures, performing an etch back process so that the top surfaces of the line structures and the dielectric layer are flush, forming layer structure with same material as the line structures on the line structures and the dielectric layer, forming spacers spaced apart from each other in a second direction on the layer structure, and performing an etch process with the spacers as an etch mask to pattern the line structures and the dielectric layer.

First claim

What is claimed is:

1. A self-aligned double patterning (SADP) method, comprising:
providing a substrate with a mask layer formed thereon;
forming a plurality of line structures on said mask layer, wherein said line structures extend in a first direction and spaced-apart from each other;
forming a dielectric layer on said line structures and said substrate;
performing an etch back process so that the top surfaces of said line structures and said dielectric layer are flush;
forming a layer structure on said line structures and said dielectric layer, wherein the material of said layer structure and said line structures are the same;
forming a plurality of spacers in a second SADP process on said layer structure, wherein the step of forming said spacers in said second SADP process comprises:
forming a plurality of mandrels on said layer structure, wherein said mandrels extend in said second direction and spaced-apart from each other;
forming a conformal spacer layer on said mandrels and said layer structure; and
performing an anisotropic etch process to said spacer layer to form said spacers in said second SADP process, wherein said spacers in said second SADP process extend in a second direction and spaced-apart from each other; and

performing a first etch process with said spacers in said second SADP process as an etch mask to pattern said layer structure, said line structures and said dielectric layer.

2. The self-aligned double patterning method of claim 1 , wherein the step of forming said line structures comprises:
forming a plurality of mandrels and spacers in a first SADP process at two sides of each said mandrel on a material layer, wherein said spacers in said first SADP process extend in said first direction and spaced-apart from each other; and
performing a second etch process with said spacers in said first SADP process as an etch mask to pattern underlying said material layer into said line structures.

3. The self-aligned double patterning method of claim 2 , wherein said etch back process removes all said spacers in said first SADP process and parts of said dielectric layer on said line structures, so that said line structures are exposed and the top surfaces of said line structures and said dielectric layer are flush.

4. The self-aligned double patterning method of claim 2 , wherein the material of said spacers in said first SADP process and said spacers in said second SADP process is silicon oxide.

5. The self-aligned double patterning method of claim 1 , further comprising removing remaining said spacers in said second SADP process, said layer structure and said line structures after said first etch process.

6. The self-aligned double patterning method of claim 5 , further comprising performing a third etch process with remaining said dielectric layer as an etch mask to pattern underlying said mask layer and a target layer after remaining said spacers in said second SADP process, said layer structure and said line structures are removed.

7. The self-aligned double patterning method of claim 6 , further comprising removing said dielectric layer and said mask layer after patterning said target layer.

8. The self-aligned double patterning method of claim 1 , wherein said first direction is perpendicular to said second direction.

9. The self-aligned double patterning method of claim 1 , wherein the material of said layer structure and said line structures is silicon oxynitride.

10. The self-aligned double patterning method of claim 1 , wherein said dielectric layer is an organic dielectric layer.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Chang Feng-Yi
• Lee Fu-Che
• Lin Ying-Chih
• Lin Gang-Yi

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P76/4083

  characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P76/4088 Primary

  Processes for improving the resolution of the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title