Defect resistant designs for location-sensitive neural network processor arrays

Patent metadata

Field	Value
Publication number	US-12067472-B2
Application number	US-201815942298-A
Country	US
Kind code	B2
Filing date	Mar 30, 2018
Priority date	Mar 30, 2018
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

Defect resistant designs for location-sensitive neural network processor arrays are provided. In various embodiments, plurality of neural network processor cores are arrayed in a grid. The grid has a plurality of rows and a plurality of columns. A network interconnects at least those of the plurality of neural network processor cores that are adjacent within the grid. The network is adapted to bypass a defective core of the plurality of neural network processor cores by providing a connection between two non-adjacent rows or columns of the grid, and transparently routing messages between the two non-adjacent rows or columns, past the defective core.

First claim

What is claimed is:

1. A system comprising:
a plurality of neural network processor cores arrayed in a grid, the grid having a plurality of rows and a plurality of columns; and
a network interconnecting at least those of the plurality of neural network processor cores that are adjacent within the grid, wherein:
the network comprises a switchable bypass between each adjacent core along each direction of two dimensions of the grid, each switchable bypass being directly connected, by a wire, to an input of one of the plurality of neural network processor cores and an output of that one of the plurality of neural network processor cores, and to an input of an adjacent one of the plurality of neural network processor cores, and
the network is adapted to bypass a defective core of the plurality of neural network processor cores by
applying the switchable bypass to provide a connection between two of the plurality of neural network processor cores in non-adjacent rows or columns of the grid, and
transparently routing messages between the two non-adjacent rows or columns, past the defective core, via the switchable bypass.

2. The system of claim 1 , wherein:
the network comprises a loop connecting all cores within a row or column.

3. The system of claim 1 , wherein:
the network comprises a loop connecting all cores within two adjacent rows or columns.

4. The system of claim 1 , wherein the bypass comprises a multiplexor.

5. The system of claim 1 , wherein the bypass precedes each core, and is adapted to select between an input from an adjacent core and a non-adjacent core.

6. The system of claim 1 , wherein the bypass succeeds each core, and is adapted to select between an output of each core and of a preceding core.

7. The system of claim 6 , wherein the bypass is connected to a succeeding core without any additional connection between the core and the succeeding core.

8. The system of claim 1 , wherein the plurality of neural network processor cores are adapted to operate at a reduced clock frequency when bypassing a defective core.

9. The system of claim 1 , wherein each of the plurality of neural network processor cores is identified by a physical address.

10. The system of claim 9 , wherein the network is adapted to map a logical address to each of the cores, and wherein bypassing the defective core comprises remapping the logical addresses.

11. The system of claim 1 , wherein the network is adapted to deliver message between cores, based on relative addresses.

12. A system comprising:
a plurality of neural network processor cores arrayed in a grid, the grid having a plurality of rows and a plurality of columns; and
a network interconnecting at least those of the plurality of neural network processor cores that are adjacent within the grid, wherein:
the network comprises a switchable bypass between each adjacent core along each direction of two dimensions of the grid, each switchable bypass being directly connected, by a wire, to an input of one of the plurality of neural network processor cores and an output of that one of the plurality of neural network processor cores, and to an input of an adjacent one of the plurality of neural network processor cores, and
the network is adapted to bypass a defective core of the plurality of neural network processor cores by
applying the switchable bypass to provide a connection between two of the plurality of neural network processor cores in non-adjacent cores, and
transparently routing messages between the two non-adjacent cores, past the defective core, via the switchable bypass.

13. The system of claim 12 , wherein each of the plurality of neural network processor cores is identified by a physical address.

14. The system of claim 13 , wherein the network is adapted to map a logical address to each of the cores, and wherein bypassing the defective core comprises remapping the logical addresses.

15. The system of claim 12 , wherein the network is adapted to deliver message between cores, based on relative addresses.

16. A method of bypassing a defective core of a plurality of neural network processor cores, the cores being arrayed in a grid, the grid having a plurality of rows and a plurality of columns, a network interconnecting at least those of the plurality of neural network processor cores that are adjacent within the grid, wherein:
the network comprises a switchable bypass between each adjacent core, the method comprising:
directly connecting each switchable bypass, by a wire, to an input of one of the plurality of neural network processor cores and an output of that one of the plurality of neural network processor cores, and to an input of an adjacent one of the plurality of neural network processor cores;
applying the switchable bypass to provide a connection between two of the plurality of neural network processor cores in non-adjacent rows or columns of the grid along each direction of two dimensions of the grid; and
transparently routing messages between the two non-adjacent rows or columns, past the defective core, via the switchable bypass.

17. The method of claim 16 , wherein:
the network comprises a loop connecting all cores within a row or column.

18. The method of claim 16 , wherein:
the network comprises a loop connecting all cores within two adjacent rows or columns.

19. The method of claim 16 , wherein the bypass comprises a multiplexor.

20. The method of claim 16 , wherein the bypass precedes each core, and is adapted to select between an input from an adjacent core and a non-adjacent core.

21. The method of claim 16 , wherein the bypass succeeds each core, and is adapted to select between an output of each core and of a preceding core.

22. The method of claim 21 , wherein the bypass is connected to a succeeding core without any additional connection between the core and the succeeding core.

23. A method of bypassing a defective core of a plurality of neural network processor cores, the cores being arrayed in a grid, the grid having a plurality of rows and a plurality of columns, a network interconnecting at least those of the plurality of neural network processor cores that are adjacent within the grid, wherein:
the network comprises a switchable bypass between each adjacent core, the method comprising:
directly connecting each switchable bypass, by a wire, to an input of one of the plurality of neural network processor cores and an output of that one of the plurality of neural network processor cores, and to an input of an adjacent one of the plurality of neural network processor cores;
applying the switchable bypass to provide a connection between two non-adjacent cores along each direction of two dimensions of the grid; and
transparently routing messages between the two non-adjacent cores, past the defective core, via the switchable bypass.

Assignees

• IBM

Inventors

• Appuswamy Rathinakumar
• Arthur John V
• Cassidy Andrew S
• Datta Pallab
• Esser Steven K
• Flickner Myron D
• Klamo Jennifer
• Modha Dharmendra S
• Penner Hartmut
• Sawada Jun
• Taba Brian

Classifications

• G06N3/06 Primary

  Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06N3/045

  Combinations of networks · CPC title

• G06N3/048

  Activation functions · CPC title