Final faulty core recovery mechanisms for a two-dimensional network on a processor array

Patent metadata

Field	Value
Publication number	US-8990616-B2
Application number	US-201213631496-A
Country	US
Kind code	B2
Filing date	Sep 28, 2012
Priority date	Sep 28, 2012
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

Embodiments of the invention relate to faulty recovery mechanisms for a two-dimensional (2-D) network on a processor array. One embodiment comprises a processor array including multiple processors core circuits, and a redundant routing system for routing packets between the core circuits. The redundant routing system comprises multiple switches, wherein each switch corresponds to one or more core circuits of the processor array. The redundant routing system further comprises multiple data paths interconnecting the switches, and a controller for selecting one or more data paths. Each selected data path is used to bypass at least one component failure of the processor array to facilitate full operation of the processor array.

First claim

What is claimed is:

1. A processor array, comprising:
multiple processors core circuits; and
a redundant routing system for routing packets between the core circuits, wherein the redundant routing system comprises:
multiple switches, wherein each switch corresponds to one or more core circuits of the processor array;
multiple data paths interconnecting the switches, wherein said multiple data paths include at least one redundant data path interconnecting a pair of non-neighbo…

Assignees

• IBM

Inventors

• Alvarez-Icaza Rivera Rodrigo
• Arthur John V
• Barth Jr John E
• Cassidy Andrew S
• Iyer Subramanian
• Merolla Paul A
• Modha Dharmendra S

Classifications

• H04L45/28

  Electricity · mapped topic

• G06F11/2005

  Physics · mapped topic

• G06F11/2007

  Physics · mapped topic

• H04L49/1523 Primary

  Electricity · mapped topic

• H04L49/557

  Electricity · mapped topic