Semiconductor device and memory device comprising the same

Patent metadata

Field	Value
Publication number	US-12066849-B2
Application number	US-202217744067-A
Country	US
Kind code	B2
Filing date	May 13, 2022
Priority date	Aug 19, 2021
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A semiconductor device including an error amplifier configured to receive a voltage of an output node and a reference voltage, a flipped voltage follower (FVF) circuit configured to receive an output of the error amplifier and maintain the voltage of the output node at the reference voltage, and a bias current control circuit configured to receive first to third mode signals, control a magnitude of a bias current flowing through the FVF circuit based on the first to third mode signals, control the bias current of a first magnitude, based on the first mode signal, control the bias current of a second magnitude smaller than the first magnitude, based on the second mode signal, and control the bias current of a third magnitude smaller than the second magnitude, based on the third mode signal.

First claim

What is claimed is:

1. A semiconductor device comprising:
an error amplifier configured to receive a voltage of an output node and a reference voltage;
a flipped voltage follower (FVF) circuit configured to receive an output of the error amplifier and maintain the voltage of the output node at the reference voltage; and
a bias current control circuit configured to
receive a first mode signal, a second mode signal, and a third mode signal,
control a magnitude of a bias current flowing through the FVF circuit based on the first mode signal, the second mode signal, and the third mode signal,
control the bias current of a first magnitude to flow through the FVF circuit, in response to the first mode signal,
control the bias current of a second magnitude smaller than the first magnitude to flow through the FVF circuit, in response to the second mode signal, and
control the bias current of a third magnitude smaller than the second magnitude to flow through the FVF circuit, in response to the third mode signal.

2. The semiconductor device of claim 1 , wherein the bias current control circuit includes a first current source, a second current source, and a third current source,
the first current source, the second current source, and the third current source are configured to be activated in response to the first mode signal,
the first current source is configured to be deactivated and the second and third current sources are configured to be activated in response to the second mode signal, and
the first and second current sources are configured to be deactivated and the third current source is configured to be activated in response to the third mode signal.

3. The semiconductor device of claim 2 , wherein each of the first current source, the second current source, and the third current source are a current mirror.

4. The semiconductor device of claim 1 , wherein the bias current control circuit includes
a first current source configured to provide a first current of the first magnitude,
a second current source configured to provide a second current of the second magnitude, and
a third current source configured to provide current of a third magnitude,
the first current source is configured to be activated and the second and third current sources are configured to be deactivated, in response to the first mode signal,
the second current source is configured to be activated and the first and third current sources are configured to be deactivated, in response to the second mode signal, and
the third current source is configured to be activated and the first and second current sources are configured to be deactivated, in response to the third mode signal.

5. The semiconductor device of claim 1 , wherein the first mode signal, the second mode signal, and the third mode signal are configured to be determined based on a signal level of a first signal, and a signal level of a second signal different from the first signal.

6. The semiconductor device of claim 5 , wherein the second signal is configured to be generated by delaying the first signal.

7. The semiconductor device of claim 6 , wherein the first mode signal is configured to be generated in response to the first signal of a first level,
the second mode signal is configured to be generated in response to the first signal of a second level different from the first level and the second signal of the first level, and
the third mode signal is configured to be generated in response to the first signal of the second level and the second signal of the second level.

8. The semiconductor device of claim 1 , wherein the bias current control circuit is configured to receive a fourth mode signal, and
the bias current control circuit is configured to control the bias current of a fourth magnitude smaller than the third magnitude to flow through the FVF circuit, in response to the fourth mode signal.

9. A semiconductor device comprising:
an error amplifier configured to receive a voltage of an output node and a reference voltage;
a first transistor configured to maintain the voltage of the output node at the reference voltage, using a power supply voltage based on an output of the error amplifier; and
a bias current control circuit configured to
receive a first mode signal, a second mode signal, and a third mode signal,
control a magnitude of a bias current flowing through the first transistor based on the first mode signal, the second mode signal, and the third mode signal,
control the bias current of a first magnitude to flow through the first transistor, in response to the first mode signal,
control the bias current of a second magnitude smaller than the first magnitude to flow through the first transistor, in response to the second mode signal, and
control the bias current of a third magnitude smaller than the second magnitude to flow through the first transistor, in response to the third mode signal.

10. The semiconductor device of claim 9 , further comprising:
a second transistor connected between the power supply voltage and the first transistor, and having a gate electrode connected to one end of the first transistor.

11. The semiconductor device of claim 10 , further comprising:
a third transistor connected between the power supply voltage and one end of the first transistor, and having gate electrode connected to a gate electrode of the second transistor.

12. The semiconductor device of claim 11 , further comprising:
a fourth transistor connected between one end of the third transistor and one end of the first transistor.

13. The semiconductor device of claim 12 , wherein a conductive type of the fourth transistor is different from conductive types of the first transistor, the second transistor, and the third transistor.

14. The semiconductor device of claim 9 , wherein the first mode signal, the second mode signal, and the third mode signal are determined based on a signal level of a first signal, and a signal level of a second signal different from the first signal.

15. The semiconductor device of claim 14 , wherein the second signal is configured to be generated by delaying the first signal.

16. The semiconductor device of claim 15 , wherein the first mode signal is configured to be generated in response to the first signal of a first level,
the second mode signal is configured to be generated in response to the first signal of a second level different from the first level, and the second signal of the first level, and
the third mode signal is configured to be generated in response to the first signal of the second level and the second signal of the second level.

17. A memory device comprising:
a memory cell;
a data input/output buffer configured to buffer data to be written to the memory cell or buffer data read from the memory cell; and
a regulator in the data input/output buffer and is configured to receive first and second signals,
wherein the regulator includes
an error amplifier configured to receive a voltage of an output node and a reference voltage;
an FVF circuit configured to receive an output of the error amplifier and maintain the voltage of the output node at the reference voltage; and
a bias current control circuit configured to control a magnitude of a bias current flowing through the FVF circuit, the bias current control circuit being configured to
control the bias current of a first magnitude to flow through the FVF circuit, in response to the first signal of a first level,
control the bias current of a second magnitude smaller than the first magnitude to flo

Assignees

• Samsung Electronics Co Ltd

Inventors

• Roh Kyoung Jun
• Park Jae Woo
• Choi Jun Han
• Kwak Myoung Bo
• Choi Jung Hwan

Classifications

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• H03F3/45071

  with semiconductor devices only · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title