Dynamic biasing circuits for low drop out (LDO) regulators

Patent metadata

Field	Value
Publication number	US-9710002-B2
Application number	US-201514930906-A
Country	US
Kind code	B2
Filing date	Nov 3, 2015
Priority date	May 27, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Dynamic biasing circuits for low drop out (LDO) regulators are described. In some embodiments, an electronic circuit may include a low drop out (LDO) regulator; and a biasing circuit coupled to the LDO regulator, the biasing circuit configured to: monitor a first electrical current and a second electrical current; select a greater of the first or second electrical currents; and provide the selected electrical current to the LDO regulator. In other embodiments, a method may include: providing a digital core and a low drop out (LDO) regulator coupled to the digital core, wherein the digital core is configured to operate in an active mode and in a standby mode; monitoring, via a current selector circuit coupled to the LDO regulator, a first current and a second current; selecting a greater of the first or second electrical currents; and providing the selected current as a biasing current to the LDO regulator.

First claim

The invention claimed is:

1. A low drop out regulator system comprising:
(a) maximum current selector circuitry having a first input for a first current, a second input for a second current, and a bias current output for a bias current selected from the larger of the first current and the second current;
(b) a low drop out regulator including:
(i) a bias current input coupled to the bias current output;
(ii) a voltage output;
(iii) a series connection of two resistors coupled between the voltage output and a circuit ground;
(iv) an output drive transistor having a connection to a supply voltage, a connection to the voltage output, and a control input;
(v) an error amplifier having a non-inverting input coupled to a reference voltage, an inverting input coupled to between the two resistors, and an output coupled to the control input;
(vi) a first pair of transistors coupled in a current mirror having a first connection coupled to the bias current input, control inputs coupled to the bias current input, ground connections to the circuit ground, and a second connection coupled to the control input; and
(vii) a third transistor coupled between the error amplifier and circuit ground and having a control input coupled to the bias current input.

2. The system of claim 1 including a second pair of transistors coupled in a current mirror having supply connections with the supply voltage, a first connection and control inputs coupled to the second connection of the first pair of transistors, and a second connection, and the second connection being coupled to the voltage output.

3. The system of claim 1 including a fourth transistor having an emitter terminal, a base terminal coupled to the output of the error amplifier, and a collector terminal coupled to circuit ground, and current mirror circuitry coupled between the emitter terminal and the voltage source.

4. The system of claim 1 including a fourth transistor having an emitter terminal, a base terminal coupled to the output of the error amplifier, and a collector terminal coupled to circuit ground, and current mirror circuitry coupled between the emitter terminal and the voltage source and being coupled with the bias current input.

5. The system of claim 1 including a capacitor coupled between the voltage output and the circuit ground and a digital core connected to the voltage output.

6. The system of claim 1 including a bandgap and active current generator connected to the reference voltage and to one of the first current and the second current.

7. The system of claim 1 in which the first current is a standby current and the second current is an active current.

8. A low drop out regulator system comprising:
(a) maximum current selector circuitry having a first input for a first current, a second input for a second current, and a bias current output for a bias current selected from one of the first current and the second current;
(b) a low drop out regulator including:
(i) a bias current input coupled to the bias current output;
(ii) a voltage output; and
(iii) an output drive transistor having a connection to a supply voltage, a connection to the voltage output, and a control input coupled to the bias current input.

9. The system of claim 8 including an error amplifier having an input coupled to the voltage output, an input coupled to a reference voltage, and an output coupled to the control input, and a bias transistor coupled between the error amplifier and a circuit ground and having a control input coupled to the bias current input.

10. The system of claim 8 including an error amplifier having an input coupled to the voltage output, an input coupled to a reference voltage, and an output coupled to the control input, and transistor circuitry having an input coupled to the bias current input and including a transistor coupling the output of the error amplifier to the control input of the output drive transistor.

11. The system of claim 8 including an error amplifier having an input coupled to the voltage output, an input coupled to a reference voltage, and an output coupled to the control input, a bias transistor coupled between the error amplifier and a circuit ground and having a control input coupled to the bias current input, and transistor circuitry having an input coupled to the bias current input and including a transistor coupling the output of the error amplifier to the control input of the output drive transistor.

12. The system of claim 8 including a capacitor coupled between the voltage output and the circuit ground and a digital core connected to the voltage output.

13. The system of claim 8 including a bandgap and active current generator connected to the reference voltage and to one of the first current and the second current.

14. The system of claim 8 in which the first current is a standby current and the second current is an active current.

Assignees

• Texas Instruments Inc

Inventors

• Easwaran Sri Navaneethakrishnan
• Devarajan Vijayalakshmi

Classifications

• G05F1/575

  characterised by the feedback circuit · CPC title

• G05F1/465

  Internal voltage generators for integrated circuits, e.g. step down generators · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title