Frequency detector for clock data recovery

Patent metadata

Field	Value
Publication number	US-12063129-B2
Application number	US-202217665477-A
Country	US
Kind code	B2
Filing date	Feb 4, 2022
Priority date	Jun 17, 2020
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.

First claim

What is claimed is:

1. A circuit, comprising:
slicer circuitry configured to output a data signal and a first error signal based on a received signal, and a second error signal based on the received signal and a first voltage offset;
a clock and data recover (CRD) circuit, comprising,
a phase detector (PD) configured to generate a PD output based on the data signal and the first error signal,
a frequency detector (FD) configured to receive the data signal, the first error signal, and the second error signal, and to generate a FD output based on the received data signal, the received first error signal, and the received second error signal; and

control circuitry configured to generate a clock control based on the PD output and the FD output.

2. The circuit of claim 1 , wherein the first error signal includes a next data term with a feed forward equalizer (FFE) coefficient, and wherein the second error signal includes the next data term with a modified version of the FFE coefficient.

3. The circuit of claim 1 , wherein the first error signal includes a next data term with a decision feedback equalizer (DFE) coefficient, and wherein the second error signal includes the next data term with a modified version of the DFE coefficient.

4. The circuit of claim 1 , wherein:
the slicer circuitry is further configured to output a third error signal based on the received signal;
the FD is further configured to receive the third error signal and generate the FD output based further on the received third error signal;
the first error signal is expressed as: e k =sign[y k −d k+1 *(h 1 )−d k *h 0 ];
the second error signal is expressed as: e ke =sign[y k −d k+1 *(h 1 +h 1e0 )−d k *h 0 ];
the third error signal is expressed as: e kl =sign[y k −d k+1 *(h 1 +h 1l0 )−d k *h 0 ];
y k is a kth received signal;
d k+1 is a (k+1)th recovered data;
h 0 is a main cursor;
h1 is a decision feedback equalizer coefficient;
h 1e0 is an early offset relative to h1; and
h 1l0 is a late offset relative to h1.

5. The circuit of claim 1 , wherein:
the slicer circuitry is further configured to output a third error signal based on the received signal;
the FD is further configured to receive the third error signal and generate the FD output based further on the received third error signal;
the first error signal is expressed as: e k =sign[y k +y k+1 *(f 1 )−d k *h 0 ];
the second error signal is expressed as: e ke =sign[y k +y k+1 *(f 1 +f 1e0 )−d k *h 0 ];
the third error signal is expressed as: e kl =sign[y k +y k+1 *(f 1 +f 1l0 )−d k *h 0 ;
y k is a (k)th received signal;
y k+1 is a (k+1)th received signal;
d k is a (k)th recovered data;
h 0 is a main cursor;
f 1 is an FFE coefficient;
f 1e0 is an early offset relative to the FFE coefficient f 1 ; and
f 1l0 is a late offset relative to the FFE coefficient f 1 .

6. The circuit of claim 1 , wherein the slicer circuitry is further configured to output a third error signal based on the received signal, wherein:
the FD is further configured to receive the third error signal and generate the FD output based further on the received third error signal; and
the FD output represents whether a local sampling clock is too fast or too slow relative to an incoming data stream.

7. The circuit of claim 1 , wherein the slicer circuitry is further configured to output a third error signal based on the received signal, wherein the FD is further configured to receive the third error signal generate the FD output based further on the received third error signal, and wherein the FD output is:
a negative number when the first, second, and third error signals change from being above zero volts to being below zero volts; and
a positive number when the first, second, and third error signals change from being below zero volts to being above zero volts.

8. The circuit of claim 1 , wherein the FD is further configured to:
periodically compute a first frequency vote based on a voltage of the first error signal;
periodically compute a second frequency vote based on a voltage of the second error signal;
periodically determine a state based on current states of the first and second frequency votes; and
generate the FD output based on a change in the state.

9. The circuit of claim 1 , wherein the control circuitry comprises:
a first order phase path configured to track a phase difference between the received signal and a local clock based on the PD output;
a multiplier circuit configured to multiply the FD output by a first frequency path gain factor prior to a frequency lock condition, and to multiply the FD output by a second frequency path gain factor subsequent to the frequency lock condition, wherein the first frequency path gain factor is greater than the second frequency path gain factor;
a second order frequency path configured to track a frequency offset between the received signal and the local clock based on a sum of the PD output and an output of the multiplier circuit; and
a summing circuit configured to combine outputs of the first order phase path and the second order frequency path.

10. The circuit of claim 9 , wherein:
the first order phase path comprises a phase path gain circuit having a phase path gain factor; and
the first frequency path gain factor is greater than the phase path gain factor.

11. A circuit, comprising:
a plurality of slicers configured to generate a data signal, a first error signal, and a second error signal based on a received signal; and
a clock and data recovery (CDR) circuit, comprising,
a phase detector (PD) configured to generate a PD output based on the data signal, the first error signal, the second error signal, and a local clock;
a frequency detector (FD) configured to generate a FD output based on, the data signal, the first error signal and the second error signal, including to,
periodically compute a first frequency vote based on a voltage of the first error signal,
periodically compute a second frequency vote based on a voltage of the second error signal,
periodically determine a state based on current states of the first and second frequency votes, and
generate the FD output based on a change in the state; and

control circuitry configured to generate a clock control based on the PD output and the FD output.

12. The circuit of claim 11 , further comprising a decision feedback equalizer (DFE), wherein the FD is further configured to generate the FD output based further on a third error signal, and wherein the first, second, and third error signals are expressed as:
e k =sign[ y k −d k+1 *( h 1 )− d k *h 0 ];

e ke =sign[ y k −d k+1 *( h 1 +h 1e0 )− d k *h 0 ]; and

e kl =sign[ y k −d k+1 *( h 1 +h 1l0 )− d k *h 0 ];

where,
y k is a kth received signal,
d k+1 is a (k+1)th recovered data,
h 0 is a main cursor,
h1 a DFE coefficient,
h 1e0 is an early offset relative to h1, and
h 1l0 is a late offset relative to h1.

13. The circuit of claim 11 , further comprising a feed-forward equalizer (FFE), wherein the FD is further configured to generate the FD output based further on a third error signal, and wherein the first, second, and third error signals are expressed as:
e k =sign[ y k +y k+1 *( f 1 )− d k *h 0 ];

e ke =sign[ y k +y k+1 *( f 1 +f 1e0 )− d k *h 0 ]; and

e kl =sign[ y k +y k+1 *( f 1 +f 1l0 )− d k *h 0 ];

where y k is a (k)th received signal,
y k+1 is a (k+1)th received signal,
d k is a (k)th recovered data,
h 0 is a main cursor,
f 1 is an FFE co

Assignees

• Xilinx Inc

Inventors

• Zhang Hongtao
• Lin Winson
• Roldan Arianne
• Frans Yohan
• Zhang Geoff

Classifications

• H04L27/01

  Equalisers {(baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005)} · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H04L2025/0349

  as a feedback filter · CPC title

• H03L7/0812

  and where no voltage or current controlled oscillator is used · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title