Baud-rate CDR circuit and method for low power applications

Patent metadata

Field	Value
Publication number	US-9313017-B1
Application number	US-201514737330-A
Country	US
Kind code	B1
Filing date	Jun 11, 2015
Priority date	Jun 11, 2015
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

In an example, a clock data recovery (CDR) circuit for a receiver includes a timing error detector circuit, a loop filter, and a phase interpolator. The timing error detector circuit is coupled to receive, at a baud-rate, data samples and error samples for symbols received by the receiver. The timing error detector circuit is operable to generate both a timing error value and an estimated waveform value per symbol based on the data samples and the error samples. The loop filter is coupled to the timing error detector to receive timing error values. The phase interpolator is coupled to the loop filter to receive filtered timing error values, the phase interpolator operable to generate a control signal to adjust a sampling phase used to generate the data samples and the error samples.

First claim

What is claimed is:

1. A clock data recovery (CDR) circuit for a receiver, comprising:
a timing error detector circuit coupled to receive, at a baud-rate, data samples and error samples for symbols received by the receiver, the timing error detector circuit operable to generate both a timing error value and an estimated waveform value per symbol based on the data samples and the error samples;
a loop filter coupled to the timing error detector to receive timing error values; and
a phase interpolator coupled to the loop filter to receive filtered timing error values, the phase interpolator operable to generate a control signal to adjust a sampling phase used to generate the data samples and the error samples.

2. The CDR circuit of claim 1 , wherein the data samples and the error samples are samples of an analog signal output by a continuous-time equalizer.

3. The CDR circuit of claim 1 , wherein the estimated waveform value per symbol comprises a combination of at least one pre-cursor, a main cursor, and at least one post-cursor.

4. The CDR circuit of claim 3 , wherein the timing error value per symbol comprises a product of an error sample for a previous symbol and a difference between an estimated waveform value for a current symbol and an estimated waveform value for a previous symbol.

5. The CDR circuit of claim 3 , wherein the timing error detector comprises:
a residual inter-symbol interference (ISI) estimation circuit operable to generate cursor-weights per symbol by accumulating and filtering correlations between the data samples and the error samples.

6. The CDR circuit of claim 5 , wherein the residual ISI estimation circuit comprises:
a plurality of data delay elements operable to output delayed data samples;
an error delay element operable to output a delayed error sample;
a plurality of correlators operable to output a plurality of correlations comprising a correlation between a current data sample and the delayed error sample and respective correlations between the delayed data samples and a current error sample; and
an accumulation and low-pass filter circuit operable to generate the cursor-weights based on the plurality of correlations.

7. The CDR circuit of claim 6 , wherein the plurality of data delay elements comprises three data delay elements, wherein the plurality of correlators comprises four correlators, and wherein the accumulation and low-pass filter is operable to generate a pre-cursor weight for a first pre-cursor and post-cursor weights for first, second, and third post-cursors.

8. The CDR circuit of claim 1 , wherein the estimated waveform value per symbol comprises a data sample for a current symbol.

9. The CDR circuit of claim 7 , wherein the timing error value per symbol comprises a product of an error sample for a previous symbol and a difference between an estimated waveform value for a current symbol and an estimated waveform value for a previous symbol.

10. A receiver, comprising:
a continuous-time equalizer circuit coupled to receive an analog signal from a channel;
a decision circuit coupled to receive an equalized analog signal from the continuous-time equalizer and to generate data samples and error samples of the equalized analog signal at a baud-rate of symbols of the analog signal; and
a clock data recovery (CDR) circuit, comprising:
a timing error detector circuit coupled to receive the data samples and the error samples, the timing error detector circuit operable to generate both a timing error value and an estimated waveform value per symbol of the analog signal based on the data samples and the error samples;
a loop filter coupled to the timing error detector to receive timing error values; and
a phase interpolator coupled to the loop filter to receive filtered timing error values, the phase interpolator operable to provide a control signal to the decision circuit for adjusting a sampling phase used to generate the data samples and the error samples.

11. The receiver of claim 10 , wherein the estimated waveform value per symbol comprises a combination of at least one pre-cursor, a main cursor, and at least one post-cursor.

12. The receiver of claim 11 , wherein the timing error value per symbol comprises a product of an error sample for a previous symbol and a difference between an estimated waveform value for a current symbol and an estimated waveform value for a previous symbol.

13. The receiver of claim 11 , wherein the timing error detector comprises:
a residual inter-symbol interference (ISI) estimation circuit operable to generate cursor-weights per symbol by accumulating and filtering correlations between the data samples and the error samples.

14. The receiver of claim 13 , wherein the residual ISI estimation circuit comprises:
a plurality of data delay elements operable to output delayed data samples;
an error delay element operable to output a delayed error sample;
a plurality of correlators operable to output a plurality of correlations comprising a correlation between a current data sample and the delayed error sample and respective correlations between the delayed data samples and a current error sample; and
an accumulation and low-pass filter circuit operable to generate the cursor-weights based on the plurality of correlations.

15. The receiver of claim 10 , wherein the estimated waveform value per symbol comprises a data sample for a current symbol.

16. The receiver of claim 15 , wherein the timing error value per symbol comprises a product of an error sample for a previous symbol and a difference between an estimated waveform value for a current symbol and an estimated waveform value for a previous symbol.

17. A method of clock data recovery (CDR) for a receiver, comprising:
receiving, at a baud-rate, data samples and error samples for symbols of an analog signal received by the receiver;
generating both a timing error value and an estimated waveform value per symbol based on the data samples and the error samples;
filtering each timing error value; and
generating a control signal to adjust sampling phase used to generate the data samples and the error samples based on filtered timing error values.

18. The method of claim 17 , wherein the operation of generating the estimated waveform value per symbol comprises:
determining a combination of at least one pre-cursor, a main cursor, and at least one post-cursor.

19. The method of claim 18 , wherein the operation of generating the estimated waveform value per symbol further comprises:
generating cursor-weights per symbol by accumulating and filtering correlations between the data samples and the error samples.

20. The method of claim 18 , wherein the operation of generating the timing error value per symbol comprises:
determining a difference between an estimated waveform value for a current symbol and an estimated waveform value for a previous symbol; and
determining a product of an error sample for a previous symbol and the difference.

Assignees

• Xilinx Inc

Inventors

• Liao Yu
• Zhang Geoffrey
• Zhang Hongtao
• Wu Zhaoyin D
• Chang Kun-Yung

Classifications

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04L7/0029

  interpolation of received data signal · CPC title

• H04L7/0087 Primary

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04L7/0025

  interpolation of clock signal · CPC title

• H04L7/0062

  detection of error based on data decision error, e.g. Mueller type detection · CPC title