Low-power phase interpolator with wide-band operation

Patent metadata

Field	Value
Publication number	US-9698970-B1
Application number	US-201615060342-A
Country	US
Kind code	B1
Filing date	Mar 3, 2016
Priority date	Mar 3, 2016
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

An example clock delivery system includes a phase-locked loop (PLL) configured to generate a plurality of input clocks, a phase interpolator configured to receive the plurality of input clocks and generate a plurality of output clocks, and a clock data recovery (CDR) circuit configured to receive the plurality of output clocks. The phase interpolator includes a decoder having a plurality of inputs configured to receive binary codes and a respective plurality of outputs configured to output thermometer codes, and a mixer circuitry segmented into a plurality of unit circuits that are enabled or disabled based on bits of the thermometer codes.

First claim

What is claimed is:

1. A phase interpolator circuit, comprising:
a decoder having a plurality of inputs configured to receive binary codes and a respective plurality of outputs configured to output thermometer codes;
a pre-mixer configured to receive input clock signals and provide pre-mixed clock signals, the pre-mixer segmented into a plurality of unit circuits that are enabled or disabled based on bits of a first pre-mixer thermometer code of the thermometer codes;
a mixer configured to receive the pre-mixed clock signals and provide mixed clock signals, the mixer segmented into a plurality of unit circuits that are enabled or disabled based on bits of a first mixer thermometer code of the thermometer codes; and
a post-mixer configured to receive the mixed clock signals and provide output clock signals, the post-mixer segmented into a plurality of unit circuits that are enabled or disabled based on bits of a first post-mixer thermometer code of the thermometer codes.

2. The phase interpolator circuit of claim 1 , wherein each of the plurality of unit circuits of the pre-mixer, each of the plurality of unit circuits of the mixer, and each of the plurality of unit circuits of the post-mixer comprises a current-mode logic (CML) circuit, each CML circuit including a current source segmented into a plurality of current sources that are enabled or disabled based on bits of a respective second pre-mixer thermometer code, second mixer thermometer code, and second post-mixer thermometer code of the thermometer codes.

3. The phase interpolator circuit of claim 2 , wherein each CML circuit in the pre-mixer includes a capacitor bank segmented into a plurality of capacitors that are enabled or disabled based on bits of a third pre-mixer thermometer code of the thermometer codes.

4. The phase interpolator circuit of claim 2 , wherein each CML circuit in the mixer is coupled to a resistor bank segmented into a plurality of resistors that are enabled or disabled based on bits of a third mixer thermometer code of the thermometer codes.

5. The phase interpolator circuit of claim 2 , wherein the CML circuits in the pre-mixer, the mixer, and the post-mixer comprise differential transistor pairs having primary current sources, the primary current sources in the pre-mixer, the mixer, and the post-mixer enabled or disabled by the bits of the first pre-mixer thermometer code, the first mixer thermometer code, and the first post-mixer thermometer code, respectively.

6. The phase interpolator circuit of claim 5 , wherein the primary current sources in the pre-mixer, the mixer, and the post-mixer are in parallel with the segmented current sources in the pre-mixer, the mixer, and the post-mixer, respectively.

7. The phase interpolator circuit of claim 1 , further comprising:
an adaptation circuit configured to receive the pre-mixed clock signals, the mixed clock signals, and the output clock signals and to generate the binary codes in response thereto.

8. A clock delivery system, comprising:
a phase-locked loop (PLL) configured to generate a plurality of input clocks;
a phase interpolator configured to receive the plurality of input clocks and generate a plurality of output clocks; and
a clock data recovery (CDR) circuit configured to receive the plurality of output clocks;
wherein the phase interpolator includes:
a decoder having a plurality of inputs configured to receive binary codes and a respective plurality of outputs configured to output thermometer codes;
a mixer circuitry segmented into a plurality of unit circuits that are enabled or disabled based on bits of the thermometer codes.

9. The clock delivery system of claim 8 , wherein the mixer circuitry comprises:
a pre-mixer configured to receive the input clock signals and provide pre-mixed clock signals, the pre-mixer segmented into a plurality of pre-mixer unit circuits that are enabled or disabled based on bits of a first pre-mixer thermometer code of the thermometer codes;
a mixer configured to receive the pre-mixed clock signals and provide mixed clock signals, the mixer segmented into a plurality of mixer unit circuits that are enabled or disabled based on bits of a first mixer thermometer code of the thermometer codes; and
a post-mixer configured to receive the mixed clock signals and provide the output clock signals, the post-mixer segmented into a plurality of post-mixer unit circuits that are enabled or disabled based on bits of a first post-mixer thermometer code of the thermometer codes.

10. The clock delivery system of claim 9 , wherein each of the plurality of pre-mixer unit circuits of the pre-mixer, each of the plurality of mixer unit circuits of the mixer, and each of the plurality of post-mixer unit circuits of the post-mixer comprises a current-mode logic (CML) circuit, each CML circuit including a current source segmented into a plurality of current sources that are enabled or disabled based on bits of a respective second pre-mixer thermometer code, second mixer thermometer code, and second post-mixer thermometer code of the thermometer codes.

11. The clock delivery system of claim 10 , wherein each CML circuit in the pre-mixer includes a capacitor bank segmented into a plurality of capacitors that are enabled or disabled based on bits of a third pre-mixer thermometer code of the thermometer codes.

12. The clock delivery system of claim 10 , wherein each CML circuit in the mixer is coupled to a resistor bank segmented into a plurality of resistors that are enabled or disabled based on bits of a third mixer thermometer code of the thermometer codes.

13. The clock delivery system of claim 10 , wherein the CML circuits in the pre-mixer, the mixer, and the post-mixer comprise differential transistor pairs having primary current sources, the primary current sources in the pre-mixer, the mixer, and the post-mixer enabled or disabled by the bits of the first pre-mixer thermometer code, the first mixer thermometer code, and the first post-mixer thermometer code, respectively.

14. The clock delivery system of claim 13 , wherein the primary current sources in the pre-mixer, the mixer, and the post-mixer are in parallel with the segmented current sources in the pre-mixer, the mixer, and the post-mixer, respectively.

15. The clock delivery system of claim 9 , wherein the phase interpolator further comprises:
an adaptation circuit configured to receive the pre-mixed clock signals, the mixed clock signals, and the output clock signals and to generate the binary codes in response thereto.

16. A method of clock phase interpolation, comprising:
converting a plurality of binary codes into a respective plurality of thermometer codes;
pre-mixing input clock signals to provide pre-mixed clock signals;
mixing the pre-mixed clock signals to provide mixed clock signals;
post-mixing the mixed clock signals to provide output clock signals;
enabling one or more pre-mixer unit circuits based on bits of a first pre-mixer thermometer code of the thermometer codes;
enabling one or more mixer unit circuits based on bits of a first mixer thermometer code of the thermometer codes; and
enabling one or more post-mixer unit circuits based on bits of a first post-mixer thermometer code of the thermometer codes.

17. The method of claim 16 , further comprising:
enabling one or more sub-range current sources in current-mode logic (CML) circuits in the enabled pre-mixer unit circuits, the enabled mixer unit circuits, and the enabled post-mixer unit circuits based on bits of a respective second pre-mixer thermometer code, second mixer thermomet

Assignees

• Xilinx Inc

Inventors

• Cho Junho

Classifications

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H03K2005/00052

  by mixing the outputs of fixed delayed signals with each other or with the input signal · CPC title

• H03L7/081

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title

• H03K5/131 Primary

  Digitally controlled · CPC title