Semiconductor packages including recesses to contain solder

Patent metadata

Field	Value
Publication number	US-12062589-B2
Application number	US-202117361823-A
Country	US
Kind code	B2
Filing date	Jun 29, 2021
Priority date	Jun 29, 2021
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

One example of a semiconductor package includes a first substrate, a second substrate, a semiconductor die, and a spacer. The semiconductor die is attached to the first substrate. The spacer is attached to the semiconductor die and attached to the second substrate via solder. A surface of the second substrate facing the spacer includes a plurality of recesses extending from proximate at least one edge of the spacer to contain a portion of the solder.

First claim

The invention claimed is:

1. A semiconductor package comprising:
a first substrate;
a second substrate;
a semiconductor die attached to the first substrate; and
a spacer attached to the semiconductor die and attached to the second substrate via solder,
wherein a surface of the second substrate facing the spacer comprises a plurality of spaced apart recesses extending from proximate at least one edge of the spacer to contain a portion of the solder; and
wherein the plurality of recesses do not extend directly between the spacer and the second substrate.

2. The semiconductor package of claim 1 , wherein at least one of the plurality of recesses extends perpendicular to the at least one edge of the spacer.

3. The semiconductor package of claim 1 , wherein at least one of the plurality of recesses extends radially from the spacer.

4. The semiconductor package of claim 1 , wherein the surface of the second substrate facing the spacer comprises a first plurality of recesses extending from proximate a first edge of the spacer and a second plurality of recesses extending from proximate a second edge of the spacer.

5. The semiconductor package of claim 1 , wherein the second substrate comprises a first metal layer, a second metal layer, and a dielectric layer between the first metal layer and the second metal layer, the first metal layer facing the spacer, and the plurality of recesses formed in the first metal layer.

6. The semiconductor package of claim 5 , wherein each recess of the plurality of recesses partially extends into the first metal layer toward the dielectric layer.

7. The semiconductor package of claim 5 , wherein each recess of the plurality of recesses extends completely through the first metal layer to the dielectric layer.

8. The semiconductor package of claim 1 , wherein each recess of the plurality of recesses comprises a depth, a width, and a length, wherein the length is greater than the depth and the width.

9. The semiconductor package of claim 1 , wherein the semiconductor die comprises contacts pads facing the second substrate, and
wherein the plurality of recesses are arranged to extend over the contact pads.

10. The semiconductor package of claim 1 , wherein a surface of the first substrate facing the semiconductor die comprises a plurality of recesses extending from proximate at least one edge of the semiconductor die.

11. A semiconductor package comprising:
a first direct bonded copper (DBC) substrate;
a second DBC substrate;
a semiconductor die attached to the first DBC substrate; and
a spacer attached to the semiconductor die and attached to the second DBC substrate via solder,
wherein a copper layer of the second DBC substrate facing the spacer comprises a plurality of recesses comprising at least one first recess extending from proximate a first edge of the spacer and at least one second recess extending from proximate a second edge of the spacer perpendicular to the first edge of the spacer to contain a portion of the solder; and
wherein the at least one first recess intersects the at least one second recess directly between the spacer and the second substrate.

12. The semiconductor package of claim 11 , wherein the copper layer of the second DBC substrate facing the spacer comprises a plurality of recesses extending from proximate a plurality of edges of the spacer.

13. The semiconductor package of claim 11 , wherein each recess of the plurality of recesses partially extends into the copper layer of the DBC substrate facing the spacer.

14. The semiconductor package of claim 11 , wherein each recess of the plurality of recesses extends completely through the copper layer of the DBC substrate facing the spacer.

15. The semiconductor package of claim 11 , wherein the semiconductor package comprises a double sided cooling package.

16. A method for fabricating a semiconductor package, the method comprising:
attaching a semiconductor die to a first substrate;
attaching a spacer to the semiconductor die; and
soldering a second substrate to the spacer such that a plurality of spaced apart recesses in a surface of the second substrate facing the spacer extend from proximate a first edge of the spacer and do not extend directly between the spacer and the second substrate.

17. The method of claim 16 , wherein during soldering, solder flows into the plurality of recesses.

18. The method of claim 16 , wherein the second substrate is soldered to the spacer with the second substrate above the spacer.

19. The method of claim 16 , wherein the second substrate is soldered to the spacer with the spacer above the second substrate.

20. The method of claim 16 , wherein soldering the second substrate to the spacer comprises soldering the second substrate to the spacer such that the plurality of recesses in the surface of the second substrate facing the spacer extend from proximate a plurality of edges of the spacer.

Assignees

• Infineon Technologies Ag

Inventors

• Lis Adrian
• Ledutke Michael

Classifications

• H10W70/02

  of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W40/255

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

• H10W40/70

  Fillings or auxiliary members in containers or in encapsulations for thermal protection or control · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W40/22 Primary

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title