ESD protection circuit with isolated SCR for negative voltage operation

Patent metadata

Field	Value
Publication number	US-12057443-B2
Application number	US-202217687380-A
Country	US
Kind code	B2
Filing date	Mar 4, 2022
Priority date	Nov 2, 2012
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

A semiconductor controlled rectifier (FIG. 4 A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region ( 100 ) having a first conductivity type (N) and a first heavily doped region ( 108 ) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region ( 104 ) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region ( 114 ) having the first conductivity type is formed within the second lightly doped region. A buried layer ( 101 ) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region ( 102 ) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region ( 400 ) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate of a second conductivity type; and
a semiconductor controlled rectifier including:
a first doped region having a first conductivity type;
a second doped region having the second conductivity type formed within the first doped region;
a third doped region having the second conductivity type formed proximate the first doped region;
a fourth doped region having the first conductivity type formed within the third doped region, wherein:
the fourth doped region has a first side abutting a shallow trench isolation structure formed in the third doped region and a second side opposite the first side;

a buried layer having the first conductivity type formed in the semiconductor substrate below the third doped region and electrically connected to the first doped region, wherein the first doped region extends to the buried layer; and
a silicide blocking layer over a junction between the first doped region and the third doped region.

2. The semiconductor device of claim 1 , further comprising:
a seventh doped region having the first conductivity type and electrically connected to the second doped region and the first doped region; and
an eighth doped region having the second conductivity type and electrically connected to the fourth doped region and the third doped region.

3. The semiconductor device of claim 1 , wherein the third doped region is electrically isolated from the semiconductor substrate by the first doped region and the buried layer.

4. The semiconductor device of claim 1 , wherein the second doped region is more heavily doped than the third doped region.

5. The semiconductor device of claim 1 , wherein the fourth doped region is more heavily doped than the first doped region.

6. The semiconductor device of claim 1 , wherein the silicide blocking layer is directly on a surface of the semiconductor substrate and comprises a deposited dielectric.

7. A semiconductor device, comprising:
a p-type semiconductor substrate; and
a semiconductor controlled rectifier including:
a first n-type doped region;
a first p-type doped region formed within the first n-type doped region;
a second p-type doped region formed proximate the first n-type doped region;
a second n-type doped region formed within the second p-type doped region, wherein:
the second n-type doped region has a first side abutting a shallow trench isolation structure formed in the second p-doped region and a second side opposite the first side;

a n-type buried layer formed in the p-type semiconductor substrate below the second p-type doped region and electrically connected to the first n-type doped region, wherein the first n-type doped region extends to the n-type buried layer; and
a silicide blocking layer over a junction between the first n-type doped region and the second p-type doped region.

8. The semiconductor device of claim 7 , further comprising:
a third n-type doped region electrically connected to the first p-type doped region and the first n-type doped region; and
a third p-type doped region electrically connected to the second n-type doped region and the second p-type doped region.

9. The semiconductor device of claim 7 , wherein the second p-type doped region is electrically isolated from the p-type semiconductor substrate by the first n-type doped region and the n-type buried layer.

10. The semiconductor device of claim 7 , wherein the first p-type doped region is more heavily doped than the second p-type doped region.

11. The semiconductor device of claim 7 , wherein the second n-type doped region is more heavily doped than the first n-type doped region.

12. The semiconductor device of claim 7 , wherein the silicide blocking layer is directly on a surface of the p-type semiconductor substrate and comprises a deposited dielectric.

13. A semiconductor device, comprising:
a p-type semiconductor substrate; and
a semiconductor controlled rectifier including:
a first n-type doped region;
a first p-type doped region formed within the first n-type doped region;
a second p-type doped region formed proximate the first n-type doped region;
a second n-type doped region formed within the second p-type doped region, wherein:
the second n-type doped region has a first side abutting a shallow trench isolation structure formed in the second p-doped region and a second side opposite the first side;

an n-type buried layer formed in the p-type semiconductor substrate below the second p-type doped region and electrically connected to the first n-type doped region, wherein the first n-type doped region extends to the n-type buried layer; and
a silicide blocking layer over a junction between the first n-type doped region and the second p-type doped region, wherein the silicide blocking layer is directly on a surface of the p-type semiconductor substrate and comprises a deposited dielectric.

14. The semiconductor device of claim 13 , further comprising:
a third n-type doped region electrically connected to the first p-type doped region and the first n-type doped region; and
a third p-type doped region electrically connected to the second n-type doped region and the second p-type doped region.

15. The semiconductor device of claim 13 , wherein the second p-type doped region is electrically isolated from the p-type semiconductor substrate by the first n-type doped region and the n-type buried layer.

16. The semiconductor device of claim 13 , wherein the first p-type doped region is more heavily doped than the second p-type doped region.

17. The semiconductor device of claim 13 , wherein the second n-type doped region is more heavily doped than the first n-type doped region.

Assignees

• Texas Instruments Inc

Inventors

• Salman Akram A
• Farbiz Farzan
• Chatterjee Amitava
• Wu Xiaoju

Classifications

• H10D62/192

  Base regions of thyristors · CPC title

• H10D18/251 Primary

  Lateral thyristors · CPC title

• H10D18/211

  having built-in localised breakdown or breakover regions, e.g. self-protected against destructive spontaneous firing · CPC title

• H10D89/713 Primary

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H01L29/7436

  Electricity · mapped topic