Memory system and method for managing number of read operations using two counters

Patent metadata

Field	Value
Publication number	US-12050812-B2
Application number	US-202318318078-A
Country	US
Kind code	B2
Filing date	May 16, 2023
Priority date	Oct 29, 2019
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.

First claim

What is claimed is:

1. A memory system comprising:
a nonvolatile memory including a memory cell array that includes a plurality of first units and at least one second unit, the second unit including the plurality of first units, the plurality of first units including at least a third unit; and
a controller configured to:
manage a plurality of first counts, each of the plurality of first counts indicating the number of read operations performed on one of the plurality of first units,
in response to a read operation being executed on the third unit and the first count for the third unit reaching a first threshold value, update a second count for the second unit, and
in response to the second count reaching a second threshold value, determine whether to execute a first operation for checking quality of data stored in at least one of the plurality of first units included in the second unit.

2. The memory system according to claim 1 ,
wherein the controller includes:
at least one first counter configured to manage the first count for the third unit, and
at least one second counter configured to manage the second count.

3. The memory system according to claim 2 ,
wherein the at least one second unit is one of a plurality of second units,
the at least one first counter is one of a plurality of first counters, the number of first counters included in the controller being equal to the number of first units, and
the at least one second counter is one of a plurality of second counters, the number of second counters included in the controller being equal to the number of second units.

4. The memory system according to claim 2 ,
wherein the at least one first counter is one of a plurality of first counters, the number of first counters included in the controller being smaller than the number of first units, and
wherein the controller is configured to, upon dynamically selecting, from among the plurality of first units, a first unit as a target for a read operation, dynamically alter, from among the plurality of first units, a first unit as a target for managing the first count managed by one of the plurality of first counters.

5. The memory system according to claim 1 ,
wherein the controller is further configured to, in the first operation,
read the data stored in the at least one of the plurality of first units included in the second unit,
count the number of fail bits in the read data, and
according to the counted number, determine whether to rewrite the data stored in the at least one of the plurality of first units included in the second unit.

6. The memory system according to claim 1 ,
wherein the controller is further configured to, in the first operation,
read the data stored in the at least one of the plurality of first units included in the second unit,
attempt to correct an error bit in the read data, and
according to whether or not the error bit is corrected, determine whether to rewrite the data stored in the at least one of the plurality of first units included in the second unit.

7. The memory system according to claim 1 ,
wherein each of the plurality of first counts is indicated by a first data size, and
wherein the second count is indicated by a second data size, the second data size being larger than the first data size.

8. The memory system according to claim 1 ,
wherein the nonvolatile memory includes a plurality of physical blocks in the memory cell array,
wherein the first unit corresponds to one of the plurality of physical blocks, and
wherein the second unit corresponds to a super block that includes at least two of the plurality of physical blocks.

9. The memory system according to claim 1 ,
wherein the at least one second unit is one of a plurality of second units and the memory cell array further includes at least one fourth unit, the fourth unit including the plurality of the second units,
wherein the controller is further configured to update a third count for the fourth unit, in response to the second count for one second unit among the plurality of second units reaching a third threshold value, and
wherein the controller is further configured to determine whether to execute a second operation for checking quality of data stored in at least one of the second units included in the fourth unit, in response to the third count reaching a fourth threshold value.

10. The memory system according to claim 9 ,
wherein the nonvolatile memory includes one or more physical blocks in the memory cell array, and each of the one or more physical blocks includes a plurality of physical word lines,
wherein the first unit corresponds to a physical word line of the plurality of physical word lines,
wherein the second unit corresponds to a logical word line, the logical word line including the plurality of physical word lines, and
wherein the fourth unit corresponds to a super block, the super block including a plurality of the logical word lines.

11. The memory system according to claim 1 ,
wherein the nonvolatile memory includes one or more physical blocks in the memory cell array, and each of the one or more physical blocks includes a plurality of physical word lines,
wherein the first unit corresponds to a physical word line of the plurality of physical word lines, and
wherein the second unit corresponds to a logical word line, the logical word line including the plurality of physical word lines.

12. The memory system according to claim 1 ,
wherein at least one of the first threshold value or the second threshold value is changed according to the number of data erase operations performed on the plurality of first units.

13. The memory system according to claim 1 ,
wherein the plurality of first units further includes a fifth unit and a sixth unit,
wherein each of the plurality of first units includes a plurality of word lines each connecting a plurality of memory cells,
wherein the fifth unit includes at least one word line that connects the plurality of memory cells all of which are in an erased state, the sixth unit does not include any one word line that connects the plurality of memory cells all of which are in the erased state, and
the controller is configured to:
in response to a read operation being performed on the fifth unit, increase the first count for the fifth unit by a first increment value; and
in response to a read operation being performed on the sixth unit, increase the first count for the sixth unit by a second increment value smaller than the first increment value.

14. A memory system comprising:
a nonvolatile memory including a memory cell array that includes a plurality of first units and at least one second unit, the second unit including the plurality of first units, the plurality of first units including at least a third unit; and
a controller configured to:
manage a plurality of first counts, each of the plurality of first counts indicating the number of read operations performed on one of the plurality of first units, and
in response to a read operation being executed on the third unit and the first count for the third unit reaching a first threshold value, update a second count for the second unit, and
in response to a total value of the first count for the third unit and the second count reaching a second threshold value, determine whether to execute a first operation for checking quality of data stored in at least one of the plurality of first units included in the second unit.

15. A method of controlling a nonvolatile memory that includes a memory cell array, the memory cell array including a plurality of

Assignees

• Kioxia Corp

Inventors

• Nishikawa Suguru
• Kojima Yoshihisa
• Amaki Takehiko

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title