Memory refresh methods and apparatuses

Patent metadata

Field	Value
Publication number	US-2016019974-A1
Application number	US-201514867985-A
Country	US
Kind code	A1
Filing date	Sep 28, 2015
Priority date	Aug 31, 2011
Publication date	Jan 21, 2016
Grant date	—

Abstract

Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.

First claim

1 . A method comprising:
determining whether a number of memory page reads exceeds a first threshold; checking additional portions of the memory for errors, during operation of the memory, after the number of pages of the memory have been read; if the number of memory page reads exceeds the first threshold or the additional portions of the memory includes a number of errors that exceeds a second threshold, reading data stored in a particular number of memory pages of a block of memory or the additional portions of the memory; and if a number of errors in the read data exceeds a third threshold, marking the block of the memory or the additional portions of the memory for refresh.

2 . The method of claim 1 , wherein determining whether a number of memory page reads exceeds a threshold comprises:
incrementing an up-counter responsive to reading a page of memory; and
determining whether a value of the incremented up-counter exceeds a particular value.

3 . The method of claim 1 , wherein determining whether a number of memory page reads exceeds a threshold comprises:
decrementing a down-counter responsive to reading a page of memory; and
determining whether a value of the decremented down-counter is below a particular value.

4 . The method of claim 1 , wherein reading data stored in a particular number of memory pages of a block of memory comprises reading data stored in a particular number of memory pages of an identified block of memory.

5 . The method of claim 4 , wherein reading data stored in a particular number of memory pages of an identified block of memory comprises reading data stored in a particular number of memory pages of a single identified block of memory.

6 . The method of claim 4 , wherein reading data stored in a particular number of memory pages of an identified block of memory comprises reading data stored in a particular number of memory pages of a block of memory identified by a refresh block pointer.

7 . The method of claim 1 , wherein marking the block of memory for refresh comprises marking the block of memory for refresh if a number of errors in any page of the read data exceeds a threshold.

8 . The method of claim 1 , further comprising receiving a plurality of page read commands.

9 . The method of claim 8 , further comprising counting a quantity of the plurality of received page read commands.

10 . An apparatus, comprising:
a plurality of pages of non-volatile memory; and a controller coupled to the plurality of pages of non-volatile memory, the controller configured to determine whether a number of memory page reads exceeds a first threshold, check additional portions of the pages of memory for errors, during operation of the memory, after the number of pages of the memory have been read, if the number of memory page reads exceeds the first threshold or the additional portions of the pages of memory include a number of errors that exceeds a second threshold, the controller is configured to read data stored in a particular number of the plurality of pages of memory of a block of memory or the additional portions of the pages of memory, and the controller further configured to determine if a number of errors in the read data exceeds a third threshold, mark the block of the memory or the additional portions of the memory for background refresh.

11 . The apparatus of claim 10 , wherein the plurality of pages of non-volatile memory are disposed in a flash memory card.

12 . The apparatus of claim 10 , wherein the controller is further configured to store in memory the current block and page being read as part of the refresh.

13 . The apparatus of claim 10 , wherein the controller is further configured to store an address of the block of memory marked for background refresh in nonvolatile memory.

14 . The apparatus of claim 13 , wherein the controller is further configured to store an address of a page location pointing to the block of memory marked for background refresh in volatile memory.

15 . The apparatus of claim 14 , wherein the controller is further configured to restart a background refresh method in response to a power cycle, wherein the controller is configured to begin the refresh at the address stored in nonvolatile memory.

16 . A controller configured to determine whether a number of memory page reads exceeds a first threshold, check additional portions of a plurality of pages of memory for errors, during operation of the plurality of pages of memory, after the number of pages of memory have been read, if the number of memory page reads exceeds the first threshold or the additional portions of the pages of memory include a number of errors that exceeds a second threshold, the controller is configured to read data stored in a particular number of the plurality of pages of memory of a block of memory or the additional portions of the pages of memory, and the controller further configured to determine if a number of errors in the read data exceeds a third threshold, mark the block of the memory or the additional portions of the memory for background refresh.

17 . The controller of claim 16 , wherein the controller is coupled to an array of multi-level nonvolatile memory cells.

18 . The controller of claim 16 , wherein the controller is further configured to use error correction code data associated with user data read from a portion of the plurality of pages of memory to determine whether errors are present in the read user data.

19 . The controller of claim 16 , wherein the controller is further configured to store a refresh block pointer identifying a block of the plurality of pages of memory not yet checked for errors.

20 . The controller of claim 16 , wherein the controller is further configured to refresh at a rate of refresh that avoids uncorrectable read disturb errors in the plurality of pages of memory before refresh occurs.

Assignees

• Micron Technology Inc

Inventors

• Blodgett Greg A

Classifications

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F11/1417

  Boot up procedures · CPC title

• G11C16/3418 Primary

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/0727 Primary

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title