Three-dimensional memory device containing bond pad-based power supply network for a source line and methods of making the same

Patent metadata

Field	Value
Publication number	US-10748894-B2
Application number	US-201916251954-A
Country	US
Kind code	B2
Filing date	Jan 18, 2019
Priority date	Jan 18, 2019
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

A memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, source regions located on, or in, the substrate, and at least one memory-side bonding pad electrically connected to the source regions. A logic die includes a power supply circuit configured to generate a supply voltage for the source regions, and at least one logic-side bonding pad electrically connected to the power supply circuit through a network of logic-side metal interconnect structures. The memory die is bonded to the logic die. The network of logic-side metal interconnect structures distributes source power from the power supply circuit over an entire area of the memory stack structures and transmits the source power to the memory die through bonded pairs of memory-side bonding pads and logic-side bonding pads.

First claim

What is claimed is:

1. A bonded assembly comprising a memory die bonded to a logic die, wherein:
the memory die comprises:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;
source regions located on or in the substrate;
source contact structures vertically extending through the alternating stack and contacting the source regions; and
at least one memory-side bonding pad electrically connected to the source contact structures through a subset of memory-side metal interconnect structures; and

the logic die comprises:
a power supply circuit configured to generate a supply voltage for the source regions; and
at least one logic-side bonding pad electrically connected to the power supply circuit through a network of logic-side metal interconnect structures and bonded to the at least one memory-side bonding pad.

2. The bonded assembly of claim 1 , wherein the at least one logic-side bonding pad is bonded to the at least one memory-side bonding pad through metal-to-metal bonding.

3. The bonded assembly of claim 1 , wherein the at least one memory-side bonding pad comprises a mesh.

4. The bonded assembly of claim 3 , wherein the mesh comprises a continuous metallic plate having an array of openings therethrough.

5. The bonded assembly of claim 1 , wherein:
the at least one memory-side bonding pad comprises an array of memory-side bonding pads; and
the at least one logic-side bonding pad comprises an array of logic-side bonding pads.

6. The bonded assembly of claim 5 , wherein:
the array of memory-side bonding pads is arranged as a two-dimensional periodic array of memory-side bonding pads extending over an area of the memory stack structures; and
the array of logic-side bonding pads is arranged as a two-dimensional periodic array of logic-side bonding pads having a same two-dimensional periodicity as the two-dimensional periodic array of memory-side bonding pads.

7. The bonded assembly of claim 6 , wherein each logic-side bonding pad within the array of logic-side bonding pads is in contact with a set of four memory-side bonding pads among the array of memory-side bonding pads.

8. The bonded assembly of claim 6 , wherein:
each of the two-dimensional periodic array of memory-side bonding pads and the two-dimensional periodic array of logic-side bonding pads comprises a periodic rectangular array having a first pitch along a first horizontal direction and a second pitch along a second horizontal direction; and
the two-dimensional periodic array of memory-side bonding pads is laterally offset from the two-dimensional periodic array of logic-side bonding pads by one half of the first pitch along the first horizontal direction and by one half of the second pitch along the second horizontal direction.

9. The bonded assembly of claim 8 , wherein:
each of the memory-side bonding pads and the logic-side bonding pads has a respective H-shaped contact-side surface that contains a pair of rail portions extending along a horizontal direction and a connecting portion extending middle sections of the rail portions; and
four edge sections of the rail portions of each of the memory-side bonding pads contacts four edge sections of rail portions of four different logic-side bonding pads.

10. The bonded assembly of claim 1 , wherein:
the memory die comprises bit lines located between the memory stack structures and the at least one memory-side bonding pad, and comprises first additional memory-side bonding pads electrically connected to the bit lines and located in a region laterally offset from the memory stack structures; and
the logic die comprises first additional logic-side bonding pads bonded to the first additional memory-side bonding pads, and comprises a sense circuit including nodes that are electrically connected to a respective one of the first additional logic-side bonding pads.

11. The bonded assembly of claim 10 , wherein:
the memory die comprises word line contact via structures contacting a respective one of the electrically conducive layers, and comprises second additional memory-side bonding pads electrically connected to a respective one of the word line contact via structures and located in another region laterally offset from the memory stack structures; and
the logic die comprises second additional logic-side bonding pads bonded to the second additional memory-side bonding pads, and comprises a word line driver circuit including nodes that are electrically connected to a respective one of the second additional logic-side bonding pads.

12. The bonded assembly of claim 1 , wherein each memory film comprises a layer stack including:
a charge storage layer comprising a charge storage material; and
a tunneling dielectric contacting the charge storage layer and a respective one of the vertical semiconductor channels.

13. The bonded assembly of claim 1 , wherein:
the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layer within the alternating stack;
the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack; and
support pillar structures extend through the stepped surfaces and through a retro-stepped dielectric material portion that overlies the stepped surfaces.

14. A method of forming a bonded assembly, comprising:
providing a memory die that comprises:
an alternating stack of insulating layers and electrically conductive layers located over a substrate,
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel,
source regions located on, or in, the substrate,
source contact structures vertically extending through the alternating stack and contacting the source regions, and
at least one memory-side bonding pad electrically connected to the source contact structures through a subset of memory-side metal interconnect structures;

a power supply circuit configured to generate a supply voltage for the source regions, and
at least one logic-side bonding pad electrically connected to the power supply circuit through a network of logic-side metal interconnect structures; and

bonding the at least one logic-side bonding pad to the at least one memory-side bonding pad.

15. The method of claim 14 , wherein bonding of the at least one logic-side bonding pad to the at least one memory-side bonding pad is performed by inducing metal-to-metal bonding between the at least one logic-side bonding pad and the at least one memory-side bonding pad.

16. The method of claim 14 , wherein the at least one memory-side bonding pad comprises a mesh.

17. The method of claim 16 , wherein:
the mesh comprises a continuous metallic plate having an array of openings therethrough; and
the array of openings in the continuous metallic plate comprises a two-dimensional periodic rectangular array of rectangular openings.

18. The method of claim 14 , wherein:
the at least one memory-side bonding pad comprises an array of memory-side bonding pads; and
the at least one logic-side bonding pad compri

Assignees

• Sandisk Technologies Llc

Inventors

• Chowdhury Murshed
• Kim Kwang-Ho
• Kai James
• Alsmeier Johann

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/936

  Multiple bond pads having different shapes · CPC title