Semiconductor device

Patent metadata

Field	Value
Publication number	US-12046599-B2
Application number	US-202117522051-A
Country	US
Kind code	B2
Filing date	Nov 9, 2021
Priority date	Mar 15, 2021
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A semiconductor device includes a substrate having first and second active regions. A first active pattern is on the first active region and includes first source/drain patterns and a first channel pattern therebetween. A second active pattern is on the second active region and includes second source/drain patterns and a second channel pattern therebetween. A gate electrode includes a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern. A gate cutting pattern is between the first and second gate electrodes and separates the first and second gate electrodes from each other. A pair of gate spacers is on opposite sidewalls of the first gate electrode extending along opposite sidewalls of the gate cutting pattern towards the second gate electrode. The gate cutting pattern includes first to third parts having maximum widths that increase from the first to the third part.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate that includes a first active region and a second active region;
a first active pattern on the first active region, the first active pattern including a pair of first source/drain patterns and a first channel pattern between the pair of first source/drain patterns;
a second active pattern on the second active region, the second active pattern including a pair of second source/drain patterns and a second channel pattern between the pair of second source/drain patterns;
a gate electrode including a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern;
a gate cutting pattern between the first gate electrode and the second gate electrode, the gate cutting pattern separating the first and second gate electrodes from each other; and
a pair of gate spacers on opposite sidewalls of the gate electrode,
wherein the pair of gate spacers extends from opposite sidewalls of the first gate electrode along opposite sidewalls of the gate cutting pattern towards opposite sidewalls of the second gate electrode,
wherein the gate cutting pattern includes:
a first part between the pair of gate spacers;
a second part on the first part; and
a third part on the pair of gate spacers,

wherein the second part lies between and connects the first part and the third part,
wherein a maximum width of the second part is greater than a maximum width of the first part, and
wherein a maximum width of the third part is greater than the maximum width of the second part.

2. The semiconductor device of claim 1 , wherein each of the pair of gate spacers includes:
a first gate spacer directly contacting the first part of the gate cutting pattern; and
a second gate spacer spaced apart from the first part of the gate cutting pattern with the first gate spacer therebetween,
wherein a top surface of the second gate spacer is higher than a top surface of the first gate spacer.

3. The semiconductor device of claim 2 , wherein:
the second part of the gate cutting pattern covers the top surface of the first gate spacer; and
the third part of the gate cutting pattern covers the top surface of the second gate spacer.

4. The semiconductor device of claim 2 , wherein:
the second gate spacer of one gate spacer of the pair of gate spacers includes a first outer sidewall;
the second gate spacer of the other gate spacer of the pair of gate spacers includes a second outer sidewall; and
the maximum width of the third part is greater than a distance between the first outer sidewall and the second outer sidewall.

5. The semiconductor device of claim 2 , wherein the second part is between the second gate spacers of the pair of gate spacers.

6. The semiconductor device of claim 2 , wherein a dielectric constant of the first gate spacer is less than a dielectric constant of the second gate spacer.

7. The semiconductor device of claim 2 , wherein a thickness of the first gate spacer is greater than a thickness of the second gate spacer.

8. The semiconductor device of claim 1 , further comprising:
an active contact electrically connected to at least one of the pairs of the first and second source/drain patterns;
a gate contact electrically connected to at least one of the first and second gate electrodes; and
a first metal layer on the active contact and the gate contact,
wherein the first metal layer includes a power line, and
wherein the gate cutting pattern vertically overlaps the power line.

9. The semiconductor device of claim 1 , wherein a width of the third part of the gate cutting pattern gradually increases in a vertical direction away from the substrate.

10. The semiconductor device of claim 1 , wherein:
the first active region is an active region of a first logic cell; and
the second active region is an active region of a second logic cell adjacent to the first logic cell.

11. A semiconductor device, comprising:
a substrate that includes a first logic cell and a second logic cell that is adjacent to the first logic cell in a first direction;
a first active pattern on the first logic cell, the first active pattern including a pair of first source/drain patterns and a first channel pattern between the pair of first source/drain patterns;
a second active pattern on the second logic cell, the second active pattern including a pair of second source/drain patterns and a second channel pattern between the pair of second source/drain patterns;
a first gate electrode on the first channel pattern;
a second gate electrode on the second channel pattern, the second gate electrode is aligned in the first direction with the first gate electrode;
a gate cutting pattern on a boundary between the first logic cell and the second logic cell, the gate cutting pattern is disposed between the first gate electrode and the second gate electrode; and
a pair of gate spacers that extends in the first direction,
wherein the pair of gate spacers extends from opposite sidewalls of the first gate electrode along opposite sidewalls of the gate cutting pattern towards opposite sidewalls of the second gate electrode,
wherein each of the pair of gate spacers includes:
a first gate spacer adjacent to the first and second gate electrodes; and
a second gate spacer spaced apart from the first and second gate electrodes with the first gate spacer therebetween,

wherein a top surface of the second gate spacer is higher than a top surface of the first gate spacer, and
wherein the gate cutting pattern covers the top surface of the first gate spacer and the top surface of the second gate spacer.

12. The semiconductor device of claim 11 , wherein the gate cutting pattern includes:
a first part between the first gate spacers of the pair of gate spacers;
a second part between the second gate spacers of the pair of gate spacers; and
a third part on the pair of gate spacers,
wherein the second part lies between and connects the first part and the third part,
wherein a maximum width of the second part is greater than a maximum width of the first part, and
wherein a maximum width of the third part is greater than the maximum width of the second part.

13. The semiconductor device of claim 12 , wherein:
the second gate spacer of one gate spacer of the pair of gate spacers includes a first outer sidewall;
the second gate spacer of the other gate spacer of the pair of gate spacers includes a second outer sidewall; and
the maximum width of the third part is greater than a distance between the first outer sidewall and the second outer sidewall.

14. The semiconductor device of claim 11 , wherein:
a dielectric constant of the first gate spacer is less than a dielectric constant of the second gate spacer; and
a thickness of the first gate spacer is greater than a thickness of the second gate spacer.

15. The semiconductor device of claim 11 , wherein:
each of the first and second channel patterns includes a plurality of stacked semiconductor patterns, the stacked semiconductor patterns are vertically spaced apart from each other; and
the gate electrode is on a top surface, a bottom surface, and opposite sidewalls of each of the stacked semiconductor patterns.

16. A semiconductor device, comprising:
a substrate that includes a logic cell, the logic cell including a PMOSFET region and an NMOSFET region that are spaced apart from each other in a first direction, the logic cell having first, second, third, and fourth boundaries, wherein the first boundary and the second boundary are opposite to each other

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Cheol
• Park Jongchul
• Jung Hyunho

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0184

  Manufacturing their gate sidewall spacers · CPC title