Device with Reinforced Metal Gate Spacer and Method of Fabricating
US-2017117380-A1 · Apr 27, 2017 · US
US10734283B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10734283-B2 |
| Application number | US-201816049305-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 30, 2018 |
| Priority date | Dec 29, 2015 |
| Publication date | Aug 4, 2020 |
| Grant date | Aug 4, 2020 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a π-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a first gate structure including a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and on opposing side faces of the first cap insulating layer, and second sidewall spacers disposed on the first sidewall spacers, the first gate structure extending in a first direction; and a first protective layer formed over the first cap insulating layer, the first sidewall spacers, and the second sidewall spacers, wherein the first protective layer has a π-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction. 2. The semiconductor device of claim 1 , wherein bottoms of the leg portions are in contact with upper surfaces of the first sidewall spacers. 3. The semiconductor device of claim 1 , wherein the first cap insulating layer is made of a same material as the second sidewall spacers and is made of a different material than the first sidewall spacers. 4. The semiconductor device of claim 3 , wherein the first cap insulating layer and the second sidewall spacers are made of a silicon nitride based material. 5. The semiconductor device of claim 4 , wherein the first sidewall spacers are made of a silicon oxide based material. 6. The semiconductor device of claim 1 , wherein: the first cap insulating layer and the second sidewall spacers are made of SiN, and the first sidewall spacers are made of at least one of SiOC and SiOCN. 7. The semiconductor device of claim 6 , wherein the first protective layer is made of at least one of aluminum nitride, aluminum oxynitride, aluminum oxide, titanium oxide, and zirconium oxide. 8. A semiconductor device comprising: a first gate structure and a second gate structure, each including a gate electrode, a cap insulating layer disposed over the gate electrode, first sidewall spacers disposed on opposing side faces of the gate electrode and on opposing side faces of the cap insulating layer, and second sidewall spacers disposed on the first sidewall spacers, the first and second gate structures extending in a first direction; a source/drain epitaxial layer disposed between the first and second gate structures; a first protective layer formed over each of the cap insulating layers, the first sidewall spacers, and the second sidewall spacers for each of the first and second gate structures; a source/drain contact contacting the source/drain epitaxial layer; and a source/drain cap layer disposed on the source/drain contact, wherein the first protective layer has a π-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction. 9. The semiconductor device of claim 8 , wherein bottoms of the leg portions are in contact with upper surfaces of the first sidewall spacers. 10. The semiconductor device of claim 8 , wherein the interface between each of the bottoms of the leg portions and each of the upper surfaces of the first sidewall spacers is located above an upper surface of the source/drain contact. 11. The semiconductor device of claim 8 , wherein the cap insulating layer is made of a same material as the second sidewall spacers and is made of a different material than the first sidewall spacers. 12. The semiconductor device of claim 11 , wherein: the cap insulating layer and the second sidewall spacers are made of SiN, and the first sidewall spacers are made of at least one of SiOC and SiOCN. 13. The semiconductor device of claim 8 , wherein the first protective layer is made of at least one of aluminum nitride, aluminum oxynitride, aluminum oxide, titanium oxide, and zirconium oxide. 14. A semiconductor device comprising: a first gate structure including a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and on opposing side faces of the first cap insulating layer, and second sidewall spacers disposed on the first sidewall spacers, the first gate structure extending in a first direction; a second gate structure including a second gate electrode, third sidewall spacers disposed on opposing side faces of the second gate electrode and fourth sidewall spacers disposed on the third sidewall spacers, the second gate structure extending in the first direction; and a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers; a second protective layer formed over the second gate electrode, the third sidewall spacers, and the fourth sidewall spacers; and a gate contact contacting the second gate electrode passing through the second protective layer; and wherein the first protective layer has a It-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction. 15. The semiconductor device of claim 14 , wherein bottoms of the leg portions are in contact with upper surfaces of the first sidewall spacers. 16. The semiconductor device of claim 14 , wherein the first cap insulating layer is made of a same material as the second sidewall spacers and is made of a different material than the first sidewall spacers. 17. The semiconductor device of claim 16 , wherein the first cap insulating layer and the second sidewall spacers are made of a silicon nitride based material. 18. The semiconductor device of claim 17 , wherein the first sidewall spacers are made of a silicon oxide based material. 19. The semiconductor device of claim 14 , wherein: the first cap insulating layer and the second sidewall spacers are made of SiN, and the first sidewall spacers are made of at least one of SiOC and SiOCN. 20. The semiconductor device of claim 19 , wherein the first protective layer is made of at least one of aluminum nitride, aluminum oxynitride, aluminum oxide, titanium oxide, and zirconium oxide.
of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title
by filling conductive material into holes, grooves or trenches · CPC title
by forming self-aligned vias or self-aligned contact plugs · CPC title
passivation or protection of the electrode, e.g. using re-oxidation · CPC title
using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.