Reading of soft bits and hard bits from memory cells

Patent metadata

Field	Value
Publication number	US-12046296-B2
Application number	US-202217577716-A
Country	US
Kind code	B2
Filing date	Jan 18, 2022
Priority date	May 7, 2020
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A memory sub-system configured to execute a read command of a first type using a combine process to read soft bit data and hard bit data from memory cells. For example, a memory device is to: measure signal and noise characteristics of memory cells for the read command; calculate, based on the characteristics, an optimized voltage and two adjacent voltages that have offsets of a same amount from the optimized voltage; read the memory cells for hard bit data using the optimized voltage and for soft bit data using the two adjacent voltages; and transmit, to the processing device, a response including the hard bit data. The soft bit data can be selectively transmitted based on a classification determined from the characteristics. When a read command of a second type is executed, soft bit data is not read; and/or the signal and noise characteristics are not measured.

First claim

What is claimed is:

1. A device, comprising:
memory cells;
a read circuit configured to apply voltages to the memory cells and determine states of the memory cells under the voltages; and
a logic circuit coupled to the read circuit and configured to, in response to a command to read the memory cells:
determine, using the read circuit, signal and noise characteristics of the memory cells at a plurality of voltages;
compute a read voltage based on the signal and noise characteristics;
instruct the read circuit to determine states of the memory cells at the read voltage and two voltages identified based on the read voltage;
generate a response to the command based on the states of the memory cells at the read voltage and the two voltages identified based on the read voltage;
generate first data based on states of the memory cells at the read voltage; and
generate second data based on exclusive or (XOR) of states of the memory cells at the two voltages;

wherein the two voltages have offsets of a same predetermined amount from the read voltage.

2. The device of claim 1 , wherein the logic circuit is configured to instruct the read circuit to determine states of the memory cells at the two voltages in response to the command is of a first type; and in response to a command of a second type to read the memory cells, the logic circuit is configured to generate a response based on states of the memory cells at a corresponding read voltage without determination of states of the memory cells at two voltages identified based on the corresponding read voltage.

3. The device of claim 2 , wherein the logic circuit is configured to determine signal and noise characteristics of the memory cells to compute a read voltage in response to commands of the first type and commands of the second type; and the logic circuit is configured to, in response to a command of a third type to read the memory cells, generate a response without determining signal and noise characteristics of the memory cells.

4. The device of claim 1 , wherein the two voltages are a first pair of voltages centered at the read voltage; and the logic circuit is further configured to:
instruct the read circuit to determine second states of the memory cells at a second pair of voltages centered at the read voltage;
wherein the response is generated further based on the second states of the memory cells at the second pair of voltages.

5. The device of claim 4 , wherein during execution of the command to read the memory cells, the logic circuit is configured to:
generate third data based on exclusive or (XOR) of states of the memory cells at the second pair of voltages.

6. The device of claim 1 , wherein during execution of the command to read the memory cells, the logic circuit is configured to:
determine, based on the signal and noise characteristics, a classification of an error rate in the first data; and
determine, based on the classification, whether to transmit the second data as part of the response to the command.

7. The device of claim 6 , wherein the classification is determined in parallel with determination of states of the memory cells at the read voltage and the two voltages.

8. The device of claim 6 , wherein after the response to the command is provided from the device, the device is further operable to receive an optional request for the second data; and in response to receiving the optional request, the device is configured to provide the second data without reading the memory cells.

9. A method, comprising:
receiving a command to read memory cells in a device;
determining, in response to the command and using a circuit of the device, signal and noise characteristics of the memory cells at a plurality of voltages, including applying by the circuit the plurality of voltages to the memory cells and determining states of the memory cells under the plurality of voltages;
computing, based on the signal and noise characteristics, a read voltage;
instructing the circuit to determine states of the memory cells at the read voltage and two voltages identified based on the read voltage, and generating first data based on states of the memory cells at the read voltage;
generating a response to the command based on the states of the memory cells at the read voltage and the two voltages identified based on the read voltage; and
generating second data based on exclusive or (XOR) of states of the memory cells at the two voltages;
wherein the two voltages have offsets of a same predetermined amount from the read voltage.

10. The method of claim 9 , wherein the instructing of the circuit to determine states of the memory cells at the two voltages is in response to the command being of a first type; and in response to a command of a second type to read the memory cells, a response is generated based on states of the memory cells at a corresponding read voltage without determining of states of the memory cells at two voltages identified based on the corresponding read voltage.

11. The method of claim 10 , wherein the determining of the signal and noise characteristics of the memory cells to compute a read voltage is in response to commands of the first type and commands of the second type; and in response to a command of a third type to read the memory cells, a response is generated without determining signal and noise characteristics of the memory cells.

12. The method of claim 9 , wherein the two voltages are a first pair of voltages centered at the read voltage; and the method further comprises:
instructing the circuit to determine second states of the memory cells at a second pair of voltages centered at the read voltage; and
generating third data based on exclusive or (XOR) of states of the memory cells at the second pair of voltages;
wherein the response is generated further based on the second states of the memory cells at the second pair of voltages.

13. The method of claim 9 , wherein during execution of the command to read the memory cells, the method further comprises:
determining, based on the signal and noise characteristics and in parallel with determination of states of the memory cells at the read voltage and the two voltages, a classification of an error rate in the first data; and
determining, based on the classification, whether to transmit the second data as part of the response to the command.

14. A memory sub-system, comprising:
a processing device; and
at least one memory device, the memory device having:
memory cells formed on an integrated circuit die; and
a read circuit configured to apply voltages to the memory cells and determine states of the memory cells under the voltages;

wherein the processing device is configured to transmit a read command to the memory device; and
wherein in response to the read command, the memory device is configured to:
determine, using the read circuit, signal and noise characteristics of the memory cells at a plurality of voltages;
compute a read voltage based on the signal and noise characteristics;
instruct the read circuit to determine states of the memory cells at the read voltage and two voltages identified based on the read voltage;
generate a response to the read command based on the states of the memory cells at the read voltage and the two voltages identified based on the read voltage;
generate first data based on states of the memory cells at the read voltage; and
generate second data based on exclusive or (XOR) of states of the memory cells at the two voltages;

wherein the two voltages have offsets of a same predetermined amount from the read voltage.

Assignees

• Micron Technology Inc

Inventors

• Fitzpatrick James
• Parthasarathy Sivagnanam
• Khayat Patrick Robert
• Alhussien Abdelhakim S

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0673

  Single storage device · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G11C2211/5632

  Multilevel reading using successive approximation · CPC title