Flip-flops and scan chain circuits including the same

Patent metadata

Field	Value
Publication number	US-12044733-B2
Application number	US-202318194643-A
Country	US
Kind code	B2
Filing date	Apr 2, 2023
Priority date	Aug 17, 2022
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.

First claim

What is claimed is:

1. A flip-flop circuit, comprising:
a selection circuit having a first node and a second node, wherein the selection circuit includes,
first, second, and third P-type transistors connected in series between a power supply terminal and the first node,
fourth and fifth P-type transistors connected in series between the power supply terminal and the first node,
first and second N-type transistors connected in series between the first node and a power ground terminal,
third and fourth N-type transistors connected in series between the first node and the power ground terminal, and
a first inverter having a first inverter input terminal connected to the first node and a first inverter output terminal connected to the second node, wherein the first inverter is configured to output one of a data signal or a scan input signal to the first inverter output terminal in response to a clock signal, a signal of a third node, or a combination of the clock signal and the signal of the third node,
wherein a scan enable signal is input to gates of the first N-type transistor and the fifth P-type transistor,
wherein the data signal is input to gates of the fourth P-type transistor and the fourth N-type transistor,
wherein an inverted scan enable signal is input to gates of the third P-type transistor and the third N-type transistor, and
wherein the scan input signal is input to gates of the second P-type transistor and the second N-type transistor;
a master latch circuit connected between the second node and the third node; and
a slave latch circuit connected between the third node and a flip-flop circuit output terminal.

2. The flip-flop circuit of claim 1 , wherein the first inverter includes,
sixth and seventh P-type transistors connected in series between the power supply terminal and the second node, and
fifth and sixth N-type transistors connected in series between the second node and the power ground terminal,
wherein the clock signal is applied to a gate of the sixth P-type transistor,
wherein the first node is connected to gates of the seventh P-type transistor and the fifth N-type transistor, and
wherein the third node is connected to a gate of the sixth N-type transistor.

3. The flip-flop circuit of claim 2 , wherein the master latch circuit includes
an eighth P-type transistor connected between the power supply terminal and the second node,
seventh and eighth N-type transistors connected in series between the second node and the power ground terminal,
ninth and tenth P-type transistors connected in parallel between the power supply terminal and the third node,
ninth and tenth N-type transistors connected in series between the third node and the power ground terminal,
transistor, and
an eleventh P-type transistor connected between the power supply terminal and the fourth node,
wherein a gate of the eighth P-type transistor is connected to the third node,
wherein gates of the seventh N-type transistor, the tenth P-type transistor, and the ninth N-type transistor are connected to the clock signal,
wherein a gate of the eighth N-type transistor is connected to the fourth node, and
wherein the ninth P-type transistor, the eleventh P-type transistor, and the tenth N-type transistor are connected to the second node.

4. The flip-flop circuit of claim 2 ,
wherein a fifth node of the selection circuit connects a drain of the sixth P-type transistor to a source of the seventh P-type transistor and a sixth node of the selection circuit connects a source of the fifth N-type transistor to a drain of the sixth N-type transistor,
wherein the slave latch circuit further includes,
a twelfth P-type transistor, an eleventh N-type transistor, and a twelfth N-type transistor connected in series between the power supply terminal and the power ground terminal, wherein a seventh node connects a drain of the twelfth P-type transistor to a drain of the eleventh N-type transistor,
a thirteenth P-type transistor connected between the fifth node and the seventh node,
a thirteenth N-type transistor connected between the seventh node and the sixth node, a second inverter having an input terminal connected to the seventh node, wherein an eighth node is connected to an output terminal of the second inverter, and
a third inverter having an input terminal connected to the eighth node and an output terminal connected to the flip-flop circuit output terminal,
wherein a gate of the twelfth P-type transistor is connected to the third node,
wherein a gate of the eleventh N-type transistor is connected to the clock signal,
wherein a gate of the twelfth N-type transistor is connected to a fourth node, and
wherein gates of the thirteenth P-type transistor and the thirteenth N-type transistor are connected to the output terminal of the second inverter.

5. The flip-flop circuit of claim 1 , wherein the flip-flop circuit further includes:
an inverter chain circuit including an even number of inverters, and having an input terminal connected to the first inverter output terminal, wherein the inverter chain circuit is connected between the first inverter output terminal and the second node.

6. The flip-flop circuit of claim 1 ,
wherein the master latch circuit latches a signal of the second node responsive to a logic high state of the clock signal, and
wherein the slave latch circuit latches the signal of the second node at the flip-flop circuit output terminal.

7. A flip-flop circuit, comprising:
a selection circuit including a multiplexer, a first inverter, and a second inverter, wherein the first inverter is connected between the multiplexer and the second inverter,
wherein the multiplexer is configured to output one of a data signal or a scan input signal to a first node in response to a scan enable signal,
wherein the first inverter is connected between the first node and a second node, wherein the first inverter is configured to invert a signal of the first node to provide a first inverted signal to the second node in response to a clock signal, and
wherein the second inverter is connected between the second node and a third node,
wherein the second inverter is configured to invert the first inverted signal of the second node to provide a second inverted signal to the third node in response to the clock signal and a signal of a fourth node;
a master latch circuit connected between the third node and the fourth node; and
a slave latch circuit connected between the fourth node and a flip-flop circuit output terminal of the flip-flop circuit, so that the master latch circuit is connected between the selection circuit and the slave latch circuit.

8. The flip-flop circuit of claim 7 , wherein the first inverter includes,
first and second P-type transistors connected in series between a power supply terminal and the second node, and
a first N-type transistor connected between the second node and a power ground terminal,
wherein a gate of the first P-type transistor is connected to the clock signal; and
wherein gates of the second P-type transistor and the first N-type transistor are connected to the first node.

9. The flip-flop circuit of claim 8 , wherein the second inverter includes,
third and fourth P-type transistors connected in series between the power supply terminal and the third node, and
second and third N-type transistors connected in series between the third node and the power ground terminal,
wherein a gate of the third P-type transistor is connected to the clock signal,
wherein gates of the fourth P-type transistor and the second N-type transistor are connected to the second node, and
wherein a gate of the third N-type transistor is connected to the fourth node.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Byounggon
• Lee Dalhee
• Yang Giyoung
• Kim Minji
• Seol Taejung
• Yang Jaebeom

Classifications

• G01R31/318541 Primary

  Scan latches or cell details · CPC title

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G01R31/318536

  Scan chain arrangements, e.g. connections, test bus, analog signals · CPC title

• G01R31/318533

  using scanning techniques, e.g. LSSD, Boundary Scan, JTAG · CPC title

• G01R31/318525 Primary

  Test of flip-flops or latches · CPC title