Skew-tolerant flip-flop

Patent metadata

Field	Value
Publication number	US-9853630-B2
Application number	US-201514940563-A
Country	US
Kind code	B2
Filing date	Nov 13, 2015
Priority date	Nov 13, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A flip-flop includes a master latch configured to receive a data signal and a scan input signal. The master latch provides one of the data signal or the scan input signal to a slave latch based on a scan enable signal. The flip-flop includes circuitry configured to generate clock signals based on one or both of an input clock signal and the scan enable signal. A first clock signal is provided to the master latch and a second clock signal is provided to the slave latch. The first clock signal does not include edge transitions that occur at same times as edge transitions of the second clock signal when the scan enable signal has a first logic level. The first clock signal includes edge transitions that occur at same times as edge transitions of the second clock signal when the scan enable signal has a second logic level.

First claim

What is claimed is:

1. A flip-flop comprising:
a master latch configured to receive a data signal and a scan input signal;
a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the scan input signal to the slave latch based on a scan enable signal received by the master latch; and
circuitry configured to receive the scan enable signal and generate multiple clock signals based on one or both of an input clock signal and the scan enable signal, the clock signals including (i) a first clock signal that is provided to the master latch, and (ii) a second clock signal that is provided to the slave latch, wherein the first clock signal does not include edge transitions that occur at same times as edge transitions of the second clock signal when the scan enable signal has a first logic level, and wherein the first clock signal includes edge transitions that occur at same times as edge transitions of the second clock signal when the scan enable signal has a second logic level different from the first logic level.

2. The flip-flop of claim 1 , wherein the circuitry comprises:
a first logic gate configured to (i) receive the scan enable signal, and (ii) generate an output that varies based on a logic level of the scan enable signal; and
a second logic gate configured to generate the first or second clock signal based on the output of the first logic gate.

3. The flip-flop of claim 2 , wherein the first logic gate generates the output based on (i) a logical combination of the scan enable signal and the input clock signal, (ii) a logical combination of the scan enable signal and the first clock signal, (iii) a logical combination of an inverted version of the scan enable signal and the first clock signal, (iv) a logical combination of the scan enable signal and the second clock signal, or (v) a logical combination of the inverted version of the scan enable signal and the second clock signal.

4. The flip-flop of claim 2 , wherein the second logic gate generates the first or second clock signal based on (i) a logical combination of the output and a delayed version of the input clock signal, or (ii) a logical combination of the output and an inverted version of the input clock signal.

5. The flip-flop of claim 1 , wherein the circuitry comprises:
a first logic gate configured to (i) receive the scan enable signal, and (ii) generate an output that varies based on a logic level of the scan enable signal; and
a second logic gate configured to generate the first clock signal based on the output of the first logic gate, the first clock signal varying based on the logic level of the scan enable signal, wherein the second clock signal does not vary based on the logic level of the scan enable signal.

6. The flip-flop of claim 1 , wherein the circuitry comprises:
a first logic gate configured to (i) receive the scan enable signal, and (ii) generate an output that varies based on a logic level of the scan enable signal; and
a second logic gate configured to generate the second clock signal based on the output of the first logic gate, the second clock signal varying based on the logic level of the scan enable signal, wherein the first clock signal does not vary based on the logic level of the scan enable signal.

7. The flip-flop of claim 1 , wherein the circuitry comprises:
a first logic gate configured to (i) receive the scan enable signal, and (ii) generate an output that varies based on a logic level of the scan enable signal; and
a second logic gate configured to generate the first clock signal based on the output of the first logic gate, the first clock signal varying based on the logic level of the scan enable signal, wherein the first clock signal comprises an inverted version of the second clock signal when the scan enable signal has the second logic level, wherein the first clock signal includes edge transitions that are delayed in time in comparison to edge transitions of the second clock signal when the scan enable signal has the first logic level, and wherein the second clock signal does not vary based on the logic level of the scan enable signal.

8. The flip-flop of claim 1 , wherein the first clock signal includes edge transitions that are delayed in time in comparison to edge transitions of the second clock signal when the scan enable signal has the first logic level, and wherein the first clock signal comprises an inverted version of the second clock signal when the scan enable signal has the second logic level, the inverted version of the second clock signal being generated by manipulating a scan control in the flip-flop.

9. The flip-flop of claim 1 , wherein the first and second clock signals have non-overlapping or substantially non-overlapping clock phases when the scan enable signal has the second logic level.

10. The flip-flop of claim 1 , wherein when the scan enable signal has the second logic level, (i) a positive edge transition of the first clock signal occurs at a same time as a negative edge transition of the second clock signal, and (ii) a negative edge transition of the first clock signal occurs at a same time as a positive edge transition of the second clock signal.

11. The flip-flop of claim 1 , wherein when the scan enable signal has the first logic level, an edge transition of the first clock signal is delayed in time in comparison to an edge transition of the second clock signal.

12. The flip-flop of claim 11 , wherein when the scan enable signal has the first logic level, (i) a positive edge transition of the first clock signal is delayed in time in comparison to a negative edge transition of the second clock signal, and (ii) a negative edge transition of the first clock signal is delayed in time in comparison to a positive edge transition of the second clock signal.

13. The flip-flop of claim 1 , wherein the circuitry comprises:
a delay circuit configured to generate a delayed version of the second clock signal, wherein when the scan enable signal has the first logic level, the first clock signal is based on the delayed version of the second clock signal, and the edge transitions of the first clock signal are delayed in time in comparison to the edge transitions of the second clock signal.

14. The flip-flop of claim 1 , wherein the circuitry comprises:
an AND logic gate configured to receive the input clock signal and the scan enable signal, the AND logic gate generating a first output based on a logical combination of the input clock signal and the scan enable signal;
clock delay buffers that comprise a plurality of serially-connected inverters, the clock delay buffers being configured to receive the second clock signal and to generate a second output that is a delayed version of the second clock signal; and
a NOR logic gate configured to receive the first and second outputs, the NOR logic gate generating a third output based on a logical combination of the first and second outputs, wherein the first clock signal is based on the third output.

15. The flip-flop of claim 14 , wherein the circuitry further comprises:
a first inverter that is configured to receive the input clock signal and to generate a fourth output that is an inverted version of the input clock signal; and
a second inverter serially-coupled to the first inverter and configured to receive the fourth output and generate a fifth output that is an inverted version of the fourth output, wherein the fifth output is the second clock signal.

16. A flip-flop comprising:
a master latch configured to receive a data signal and a scan input signal;
a slave latch co

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kao Jerry Chang-Jui
• Liu Chi-Lin
• Lu Lee-Chung
• Hsieh Shang-Chih
• Lin Bor-Tyng

Classifications

• H03K2005/00019

  Variable delay · CPC title

• H03K5/133

  using a chain of active delay devices · CPC title

• H03K3/35625 Primary

  using complementary field-effect transistors · CPC title