Multibit vectored sequential with scan

Patent metadata

Field	Value
Publication number	US-10473718-B2
Application number	US-201715846047-A
Country	US
Kind code	B2
Filing date	Dec 18, 2017
Priority date	Dec 18, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

First claim

We claim:

1. An apparatus comprising:
a multi-bit sequential including a first sequential circuitry and a second sequential circuitry; and
a multi-bit scan circuitry to provide scan of data associated with the multi-bit sequential, wherein the multi-bit scan circuitry comprises a first bit-cell and a second bit-cell, wherein part of the first bit-cell of the multi-bit scan circuitry is coupled in a feedback path of the first sequential circuitry, and wherein part of the second bit-cell of the multi-bit scan circuitry is coupled in a feedback path of the second sequential circuitry.

2. The apparatus of claim 1 , wherein an output of the first bit-cell is coupled to an input of the second bit-cell.

3. The apparatus of claim 1 , wherein the multi-bit sequential comprises a clock buffer shared by the first and second sequential circuitries.

4. The apparatus of claim 1 , wherein the feedback path of the first sequential circuitry comprises a slave latch.

5. The apparatus of claim 1 , wherein the multi-bit scan circuitry comprises buffers to generate control signals, and wherein the buffers are shared by the first and second bit-cells.

6. The apparatus of claim 1 , wherein the part of the first bit-cell, of the multi-bit scan circuitry which is coupled in the feedback path of the first sequential circuitry, comprises a pass-gate.

7. An apparatus comprising:
a multi-bit quad latch with an internally coupled level-sensitive scan circuitry; and
a combinational logic coupled to an output of the multi-bit quad latch.

8. The apparatus of claim 7 , wherein the multi-bit quad latch comprises a multi-bit sequential including a first sequential circuitry and a second sequential circuitry.

9. The apparatus of claim 8 , wherein the multi-bit quad latch comprises a multi-bit scan circuitry to provide scan of data associated with the multi-bit sequential circuitry, wherein the multi-bit scan circuitry comprises a first bit-cell and a second bit-cell, wherein part of the first bit-cell of the multi-bit scan circuitry is coupled in a feedback path of the first sequential circuitry, and wherein part of the second bit-cell of the multi-bit scan circuitry is coupled in a feedback path of the second sequential circuitry.

10. The apparatus of claim 9 , wherein an output of the first bit-cell is coupled to an input of the second bit-cell.

11. The apparatus of claim 9 , wherein the multi-bit sequential comprises a clock buffer shared by the first and second sequential circuitries.

12. The apparatus of claim 9 , wherein the feedback path of the first sequential circuitry comprises a slave latch.

13. The apparatus of claim 9 , wherein the multi-bit scan circuitry comprises buffers to generate control signals, and wherein the buffers are shared by the first and second bit-cells.

14. The apparatus of claim 9 , wherein the part of the first bit-cell, of the multi-bit scan circuitry which is coupled in the feedback path of the first sequential circuitry, comprises a pass-gate.

15. A system comprising:
a memory;
a processor coupled to the memory, the processor including:
a multi-bit quad latch with an internally coupled level-sensitive scan circuitry; and
a combinational logic coupled to an output of the multi-bit quad latch; and

a wireless interface to allow the processor to communicate with another device.

16. The system of claim 15 , wherein the multi-bit quad latch comprises a multi-bit sequential including a first sequential circuitry and a second sequential circuitry.

17. The system of claim 16 , wherein the multi-bit quad latch comprises a multi-bit scan circuitry to provide scan of data associated with the multi-bit sequential circuitry, wherein the multi-bit scan circuitry comprises a first bit-cell and a second bit-cell, wherein part of the first bit-cell of the multi-bit scan circuitry is coupled in a feedback path of the first sequential circuitry, and wherein part of the second bit-cell of the multi-bit scan circuitry is coupled in a feedback path of the second sequential circuitry.

18. The system of claim 17 , wherein an output of the first bit-cell is coupled to an input of the second bit-cell.

19. The system of claim 17 , wherein the multi-bit sequential comprises a clock buffer shared by the first and second sequential circuitries.

20. The system of claim 17 , wherein the feedback path of the first sequential circuitry comprises a slave latch.

21. The system of claim 17 , wherein the multi-bit scan circuitry comprises buffers to generate control signals, and wherein the buffers are shared by the first and second bit-cells.

22. The system of claim 17 , wherein the part of the first bit-cell, of the multi-bit scan circuitry which is coupled in the feedback path of the first sequential circuitry, comprises a pass-gate.

Assignees

• Intel Corp

Inventors

• Agarwal Amit
• Krishnamurthy Ram
• Damaraju Satish
• Hsu Steven
• REALOV Simeon

Classifications

• G01R31/318541

  Scan latches or cell details · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• H03K3/0372 Primary

  of the primary-secondary type · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G01R31/31723 Primary

  Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926) · CPC title