Device, system, and method to concurrently store multiple PMON counts in a single register

Patent metadata

Field	Value
Publication number	US-12044730-B2
Application number	US-202017131477-A
Country	US
Kind code	B2
Filing date	Dec 22, 2020
Priority date	Dec 22, 2020
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

Techniques and mechanisms for providing performance monitoring information. In an embodiment, a performance monitor circuit receives a communication which indicates a format comprising multiple fields which are each to store a respective count of monitored events. A programming of the performance monitor circuit, based on the communication, designates first bits and second bits of the register to provide, respectively, a first first field and a second field according to the format. Performance monitoring subsequent to the programming successively tallies a first count of first events which occur during a first period of time, and a second count of second events which occur during a second period of time. In another embodiment, performance monitoring results in the register concurrently storing both the first count and the second count.

First claim

What is claimed is:

1. A performance monitor circuit comprising:
first circuitry to participate in a communication which provides to the performance monitor circuit an indication of a format which comprises multiple fields each to store a respective event count;
second circuitry, coupled to the first circuitry, to program the performance monitor circuit, based on the communication, to:
designate first bits of a register to provide a first field according to the format; and
designate second bits of the register to provide a second field according to the format;

third circuitry, coupled to the second circuitry, to tally, with the register:
a first count of first events which occur during a first period of time; and
a second count of second events which occur during a second period of time after the first period of time, wherein the first field and the second field concurrently store the first count and the second count.

2. The performance monitor circuit of claim 1 , wherein:
the first count is tallied with the first field; and
based on a commencement of the second period of time:
the first count is shifted from the first field to the second field; and
the second count is tallied with the first field.

3. The performance monitor circuit of claim 2 , the third circuitry further to tally, with the register, a third count of third events which occur during a third period of time after the second period of time;
wherein, based on a commencement of the third period of time:
the first count is shifted from the second field to a third field of the register; and
the second count is shifted from the first field to the second field; and
the third count is tallied with the first field.

4. The performance monitor circuit of claim 1 , wherein the second circuitry to program the performance monitor circuit based on the communication further to determine a value which represents a length of time to tally any of multiple event counts with the register.

5. The performance monitor circuit of claim 1 , wherein the second circuitry is to program the performance monitor circuit based on the communication to provide, for each of multiple registers, respective fields of the register according to the format.

6. The performance monitor circuit of claim 1 , wherein the second circuitry to program the performance monitor circuit comprises the second circuitry to set a maximum count to be tallied with one of the first field or the second field.

7. The performance monitor circuit of claim 1 , wherein the communication comprises a parameter to enable or disable a modification of data at the register.

8. The performance monitor circuit of claim 1 , the first circuitry further to participate in another communication which sends contents of the register from the performance monitor circuit, wherein the contents are to comprise multiple event counts.

9. The performance monitor circuit of claim 1 , wherein:
the first circuitry is further to participate in a second communication which provides to the performance monitor circuit a second indication of a second format; and
the second circuitry is further to reprogram the performance monitor circuit, based on the second communication, to change a designation of bits of the register to provide fields according to the second format.

10. A system comprising:
a performance monitor circuit comprising:
first circuitry to participate in a communication which provides to the performance monitor circuit an indication of a format which comprises multiple fields each to store a respective event count;
second circuitry, coupled to the first circuitry, to program the performance monitor circuit, based on the communication, to:
designate first bits of a register to provide a first field according to the format; and
designate second bits of the register to provide a second field according to the format;

third circuitry, coupled to the second circuitry, to tally, with the register:
a first count of first events which occur during a first period of time; and
a second count of second events which occur during a second period of time after the first period of time, wherein the first field and the second field concurrently store the first count and the second count; and

a display device coupled to the performance monitor circuit, the display device to display an image base on a signal communicated with the performance monitor circuit.

11. The system of claim 10 , wherein:
the first count is tallied with the first field; and
based on a commencement of the second period of time:
the first count is shifted from the first field to the second field; and
the second count is tallied with the first field.

12. The system of claim 11 , the third circuitry further to tally, with the register, a third count of third events which occur during a third period of time after the second period of time;
wherein, based on a commencement of the third period of time:
the first count is shifted from the second field to a third field of the register;
the second count is shifted from the first field to the second field; and
the third count is tallied with the first field.

13. The system of claim 10 , wherein the second circuitry to program the performance monitor circuit based on the communication further to determine a value which represents a length of time to tally any of multiple event counts with the register.

14. The system of claim 10 , wherein the second circuitry is to program the performance monitor circuit based on the communication to provide, for each of multiple registers, respective fields of the register according to the format.

15. The system of claim 10 , wherein the second circuitry to program the performance monitor circuit comprises the second circuitry to set a maximum count to be tallied with one of the first field or the second field.

16. A method comprising:
participating in a communication which provides to a performance monitor circuit an indication of a format comprising multiple fields each to store a respective event count;
based on the communication, programming the performance monitor circuit to:
designate first bits of a register to provide a first field according to the format; and
designate second bits of the register to provide a second field according to the format;

with the register, tallying a first count of first events which occur during a first period of time; and
with the register, tallying a second count of second events which occur during a second period of time after the first period of time, wherein the first field and the second field concurrently store the first count and the second count.

17. The method of claim 16 , wherein:
the first count is tallied with the first field; and
based on a commencement of the second period of time:
the first count is shifted from the first field to the second field; and
the second count is tallied with the first field.

18. The method of claim 17 , further comprising:
with the register, tallying a third count of third events which occur during a third period of time after the second period of time;
wherein, based on a commencement of the third period of time:
the first count is shifted from the second field to a third field of the register;
the second count is shifted from the first field to the second field; and
the third count is tallied with the first field.

19. The method of claim 16 , wherein programming the performance monitor circuit based on the communication is further to determine a value repr

Assignees

• Intel Corp

Inventors

• Porwal Gaurav
• Panda Subhankar
• Yigzaw Theodros
• Holm John

Classifications

• G06F11/3003

  Monitoring arrangements specially adapted to the computing system or computing system component being monitored · CPC title

• G06F2201/86

  Event-based monitoring · CPC title

• G06F11/3476

  Data logging (G06F11/14, G06F11/2205 take precedence) · CPC title

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title

• G06F9/3017

  Runtime instruction translation, e.g. macros · CPC title