Causing an interrupt based on event count

Patent metadata

Field	Value
Publication number	US-9575766-B2
Application number	US-201113991878-A
Country	US
Kind code	B2
Filing date	Dec 29, 2011
Priority date	Dec 29, 2011
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.

First claim

What is claimed is:

1. A processor comprising:
a functional unit to output a first signal in response to an occurrence of a type of event within the processor;
a first event counter to count the occurrence of the type of event within the processor, the first event counter to count the occurrence of the type of event based at least in part on the first signal output from the functional unit, the first event counter to output a second signal in response to reaching a first predefined count; and
a second event counter coupled with the functional unit and the first event counter, the second event counter to be activated in response to the second signal from the first event counter, the second event counter to cause an interrupt of the processor in response to reaching a second predefined count, wherein the first event counter comprises a first number of bits, the second event counter comprises a second number of bits, and the first number of bits is greater than the second number of bits.

2. A processor as recited in claim 1 , further comprising a reorder buffer unit that comprises the functional unit and the second event counter, wherein the functional unit is a retirement unit and the first event counter is external to the reorder buffer unit.

3. A processor as recited in claim 1 , wherein the interrupt of the processor is to cause sampling and storage of an instruction pointer in the processor.

4. A processor as recited in claim 1 , wherein the type of event is a retirement event.

5. A processor as recited in claim 1 , wherein the type of event is an instruction retired event.

6. A processor as recited in claim 1 , wherein the type of event is a branch retired event.

7. A processor as recited in claim 1 , wherein the interrupt of the processor is to cause sampling and storage of at least a portion of an architectural state of the processor.

8. A system comprising:
a memory;
a processor coupled to the memory, the processor including:
a reorder buffer unit to output a first signal in response to an occurrence of a type of event within the processor; and
an event counter external to the reorder buffer unit to count the occurrence of the type of event within the processor, the event counter to count the occurrence of the type of event based, at least in part, on the first signal output from the reorder buffer unit, the event counter to output a second signal in response to reaching a first predefined count and to cause an interrupt of the processor in response to reaching a second predefined count greater than the first predefined count, the reorder buffer unit to maintain an indication of content of the reorder buffer unit in response to the second signal.

9. A system as recited in claim 8 , wherein, in response to the interrupt, the processor is to use the indication of the content of the reorder buffer unit to store an instruction pointer.

10. A system as recited in claim 9 , further comprising micro-code to be executed to detect the instruction pointer to store based at least in part on the indication of the content of the reorder buffer unit.

11. A system as recited in claim 8 , wherein the event counter is external to the reorder buffer unit.

12. A system as recited in claim 8 , wherein the type of event is a retirement event.

13. A system as recited in claim 8 , wherein the type of event is an instruction retired event.

14. A system as recited in claim 8 , wherein the type of event is a branch retired event.

15. A system as recited in claim 8 , wherein, in response to the interrupt, the processor is to use the indication of the content of the reorder buffer unit to store at least a portion of an architectural state of the processor.

16. A method comprising:
counting, by a first event counter of a processor, an occurrence of a type of event within the processor;
outputting, by the first event counter of the processor, a first signal in response to reaching a first predefined count;
activating a second event counter in response to the first signal from the first event counter; counting, by the second event counter, the occurrence of the type of event within the processor; and
causing, by the second event counter, an interrupt of the processor in response to reaching a second predefined count, wherein the first predefined count is greater than the second predefined count.

17. A method as recited in claim 16 , further comprising sampling an instruction pointer in response to the interrupt.

18. A method as recited in claim 16 , wherein the type of event is a retirement event and a reorder buffer unit comprises the second event counter.

19. A method as recited in claim 16 , wherein the type of event is an instruction retired event.

20. A method as recited in claim 16 , wherein the type of event is a branch retired event.

21. A method as recited in claim 16 , further comprising sampling at least a portion of an architectural state of the processor.

Assignees

• Yasin Ahmad
• Irelan Peggy J
• Levy Ofer
• Ziedan Emile
• Zhou Grant
• Intel Corp

Inventors

• Yasin Ahmad
• Irelan Peggy J
• Levy Ofer
• Ziedan Emile
• Zhou Grant

Classifications

• G06F2201/88

  Monitoring involving counting · CPC title

• G06F11/3466 Primary

  Performance evaluation by tracing or monitoring · CPC title

• G06F11/3476

  Data logging (G06F11/14, G06F11/2205 take precedence) · CPC title

• G06F2201/86

  Event-based monitoring · CPC title

• G06F9/3861 Primary

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title