Generating and communicating platform event digests from a processor of a system

Patent metadata

Field	Value
Publication number	US-10025686-B2
Application number	US-201213663821-A
Country	US
Kind code	B2
Filing date	Oct 30, 2012
Priority date	Oct 30, 2012
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

In an embodiment, a processor includes a plurality of counters each to provide a count of a performance metric of at least one core of the processor, a plurality of threshold registers each to store a threshold value with respect to a corresponding one of the plurality of counters, and an event logic to generate an event digest packet including a plurality of indicators each to indicate whether an event occurred based on a corresponding threshold value and a corresponding count value. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of processor cores each comprising a pipelined processor;
a plurality of metric counters each to provide a count value of a performance metric of at least one processor core of the plurality of processor cores, the plurality of metric counters comprising a first metric counter to provide a cache misses metric;
a plurality of count threshold registers each to store a count threshold value with respect to a corresponding one of the plurality of metric counters, the plurality of metric counters and the plurality of count threshold registers to not be visible to an operating system executing on the processor; and
an internal power control unit (PCU) to manage power consumption in the processor transparently to the operating system executing on the processor, the internal PCU further to generate an event digest packet using the plurality of metric counters and the plurality of count threshold registers, the event digest packet including a plurality of indicators corresponding to a plurality of events, each indicator to uniquely indicate whether a corresponding event occurred based on a corresponding count threshold value and a corresponding count value, the event digest packet not including the corresponding count threshold value and the corresponding count value, the internal PCU further to communicate the event digest packet to a datacenter manager via a sideband interface transparently to the operating system executing on the processor.

2. The processor of claim 1 , wherein each of the plurality of indicators in the event digest packet is to indicate whether the count value of a corresponding metric counter overflowed, underflowed, or crossed a corresponding threshold value.

3. The processor of claim 1 , wherein the internal PCU is to communicate the event digest packet to the datacenter manager via a manageability engine of a peripheral controller, wherein the peripheral controller is coupled to the processor via a platform environment control interface.

4. The processor of claim 1 , wherein the internal PCU comprises a microcontroller to execute firmware instructions stored within the processor, wherein execution of the firmware instructions is not visible to the operating system executing on the processor.

5. The processor of claim 1 , wherein the internal PCU is to enable communication of the event digest packet to the datacenter manager at a periodic interval, without polling by the datacenter manager.

6. The processor of claim 1 , wherein the internal PCU is to enable communication of the event digest packet to the datacenter manager when a value of one of the plurality of indicators has changed.

7. The processor of claim 1 , wherein the plurality of count threshold registers are programmable responsive to programming information received from the datacenter manager.

8. The processor of claim 1 , wherein each indicator in the event digest packet consists of two bits that represent a ratio of the count value of corresponding counter with respect to the corresponding count threshold value.

9. The processor of claim 8 , wherein the ratio representation corresponds to a presence of the ratio within a range of ratio values.

10. The processor of claim 1 , wherein the sideband interface comprises a single wire interface.

11. The processor of claim 1 , further comprising an internal performance monitoring unit (PMU) of the processor, the internal PMU including a set of PMU metric counters, wherein the set of PMU metric counters are accessible to the operating system executing on the processor.

12. The processor of claim 1 , wherein the internal PCU is to:
receive the count values from at least some of the plurality of metric counters and the count threshold values from at least some of the plurality of count threshold registers;
generate at least one indicator responsive to detection of an event;
provide the at least one indicator to an event storage;
receive a count value from a first metric counter of the plurality of metric counters;
calculate an event responsive to the count value;
generate the event digest packet based on the at least one indicator from the event storage and the calculated event.

13. The processor of claim 1 , the plurality of metric counters comprising a set of hardware metric counters and a set of firmware metric counters, the plurality of counter threshold registers to store threshold values for the set of hardware metric counters, and the set of firmware metric counters transparently to the operating system executing on the processor.

14. A system comprising:
a plurality of servers each having a multicore processor, wherein each multicore processor includes:
a plurality of cores,
a plurality of metric counters each to provide a count value of a performance metric of at least one core,
a plurality of count threshold registers each to store a count threshold value with respect to a corresponding one of the plurality of metric counters, the plurality of metric counters and the plurality of count threshold registers to not be visible to an operating system executing on the multicore processor, and
an internal power control unit (PCU) to manage power consumption in the multicore processor transparently to the operating system executing on the multicore processor, the internal PCU further to generate an event digest packet using the plurality of metric counters and the plurality of count threshold registers, the event digest packet including a plurality of indicators corresponding to a plurality of events, each indicator to uniquely indicate whether a corresponding event occurred based on a corresponding count threshold value and a corresponding count value, the event digest packet not including the corresponding count values, the internal PCU further to communicate the event digest packet to a datacenter manager via a sideband interface transparently to the operating system executing on the multicore processor; and
a datacenter manager remotely coupled to the plurality of servers to receive the event data packet via a sideband channel from each of the plurality of servers, wherein the datacenter manager is to communicate a command to at least one of the plurality of servers to update a policy for a hardware component of the at least one server.

15. The system of claim 14 , wherein the internal PCU is to communicate the event digest packet to the datacenter manager via a manageability engine of a peripheral controller, wherein the peripheral controller is coupled to the processor via a platform environment control interface.

16. The system of claim 14 , wherein each indicator in the event digest packet comprises two bits to indicate a value based on a ratio of the corresponding count value to the corresponding count threshold value, wherein the two bits indicate a presence of the ratio within a range of ratio values.

17. The system of claim 16 , wherein the internal PCU comprises a microcontroller to execute firmware instructions stored within the processor, wherein execution of the firmware instructions is not visible to the operating system executing on the processor.

18. The system of claim 14 , wherein each multicore processor includes an internal performance monitoring unit (PMU), the internal PMU including a set of PMU metric counters.

19. The system of claim 14 , the plurality of metric counters comprising at least one metric counter to provide an interface bandwidth utilization metric.

20. The system of claim 14 , the plurality

Assignees

• Intel Corp

Inventors

• Ganguli Mrittika
• Thomas Tessil
• Rose Vinila
• Mousa Hussam
• Kumar Mohan J

Classifications

• G06F11/3433 Primary

  for load management (allocation of a server based on load conditions G06F9/505; load rebalancing G06F9/5083; redistributing the load in a network by a load balancer H04L67/1029) · CPC title

• G06F2201/83

  the solution involving signatures · CPC title

• G06F2201/88

  Monitoring involving counting · CPC title

• G06F2201/885

  Monitoring specific for caches · CPC title

• G06F2201/86

  Event-based monitoring · CPC title