Ingress data placement

Patent metadata

Field	Value
Publication number	US-9817786-B1
Application number	US-201514752294-A
Country	US
Kind code	B1
Filing date	Jun 26, 2015
Priority date	Jun 26, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Server computers often include one or more input/output (I/O) adapter devices for communicating with a network or directly attached storage device. The data transfer latency for request can be reduced by utilizing ingress data placement logic to bypass the processor of the I/O adapter device. For example, host memory descriptors can be stored in a content addressable memory unit of the I/O adapter device to facilitate placement of requested data.

First claim

What is claimed is:

1. An I/O adapter device comprising:
a content addressable memory (CAM);
a processing core configured to:
receive, from a virtual machine executing on a host device, a request for data at a storage location;
store a set of one or more CAM entries associated with the request in the CAM, each CAM entry having a key that is associated with a context entry that includes a plurality of host memory descriptors; and
send one or more request packets to the storage location to retrieve the data; and

ingress data placement circuitry configured to:
receive, from the storage location, one or more response packets corresponding to the one or more request packets, each response packet including a header and a data payload containing at least a portion of the data; and
for each response packet:
derive a lookup key, wherein the lookup key is derived by combining header fields in the header of the response packet, wherein the combination of header fields is determined based on packet information in the header of the response packet;
provide the lookup key to the CAM to retrieve the context entry associated with the key that matches the lookup key; and
provide the data payload to the host device using the retrieved context entry.

2. The I/O adapter device of claim 1 , wherein the combination of header fields is determined based on a packet type of the response packet.

3. The I/O adapter device of claim 1 , wherein the combination of header fields used to derive the lookup key is configurable.

4. The I/O adapter device of claim 1 , wherein each host memory descriptor indicates a host memory page to store at least a portion of the data payload.

5. The I/O adapter device of claim 4 , wherein each data payload is of a data payload size, each host memory page is of a host memory page size, and a number of host memory descriptors included in each context entry is equal to one plus a result of the data payload size divided by the host memory page size.

6. The I/O adapter device of claim 1 , wherein the ingress data placement circuitry is further configured to provide an indication of receiving the data payload to the processing core.

7. The I/O adapter device of claim 1 , wherein the request is a read request.

8. A computer-implemented method performed by an I/O adapter that includes a processing core and ingress data placement logic, the method comprising:
receiving, by the processing core, a request from a host device for data at a storage location;
sending, by the processing core, a request packet to the storage location to retrieve at least a portion of the data;
receiving, by the ingress data placement logic, a response packet corresponding to the request packet, the response packet including a header and a data payload containing at least the portion of the data; and
utilizing the ingress data placement logic to bypass the processing core to send the data payload to the host device by:
retrieving a host memory descriptor using a lookup key, wherein the lookup key is derived by combining header fields in the header of the response packet, wherein the combination of header fields is determined based on packet information in the header of the response packet; and
sending the data payload to the host device using the retrieved host memory descriptor.

9. The computer-implemented method of claim 8 , further comprising:
storing, by the processing core, the host memory descriptor in the I/O adapter, the host memory descriptor indicating a host memory location to store at least a portion of the data payload.

10. The computer-implemented method of claim 9 , wherein the host memory descriptor includes a host memory address and a data length.

11. The computer-implemented method of claim 8 , wherein the combination of header fields is configurable.

12. The computer-implemented method of claim 8 , wherein the combination of header fields is determined based on a packet type of the response packet.

13. The computer-implemented method of claim 8 , wherein the request is a read request.

14. The computer-implemented method of claim 8 , wherein the response packet includes a unique tag in the header that was generated by the processor core.

15. The computer-implemented method of claim 8 , wherein the packet information in the header of the response packet used for determining the combination of header fields is protocol version information.

16. An apparatus comprising:
a processor; and
ingress data placement logic,
wherein the processor is configured to:
receive, from a virtual machine, a request for data at a storage location;
store a context entry for the request, the context entry including at least one memory descriptor; and
send a request packet for the request to the storage location to retrieve at least a portion of the data, and

wherein the ingress data placement logic is configured to:
receive, from the storage location, a response packet corresponding to the request packet, the response packet including a header and a data payload containing at least the portion of the data;
retrieve the context entry using a lookup key, wherein the lookup key is derived by combining header fields in the header of the response packet, wherein the combination of header fields is determined based on packet information in the header of the response packet; and
bypass the processor to provide the data payload to the virtual machine using the context entry.

17. The apparatus of claim 16 , further comprising:
a configuration register to set which header fields are used to derive the lookup key.

18. The apparatus of claim 16 , wherein the request is a read request.

19. The apparatus of claim 16 , wherein an indication of receiving the data payload is provided to the processor after the data payload has been provided to the virtual machine.

20. The apparatus of claim 16 , wherein different types of response packets use different combinations of header fields to derive the lookup key.

Assignees

• Amazon Tech Inc

Inventors

• Khan Asif
• Volpe Thomas A
• Brooker Marc John
• Olson Marc Stephen
• Kusters Norbert Paul
• Davis Mark Bradley
• Johnson Robert Michael

Classifications

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G11C15/00

  Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores · CPC title

• G06F11/1064

  in cache or content addressable memories · CPC title

• G11C2207/2272

  Latency related aspects · CPC title