Methods of forming semiconductor packages with back side metal

Patent metadata

Field	Value
Publication number	US-12040310-B2
Application number	US-202218069257-A
Country	US
Kind code	B2
Filing date	Dec 21, 2022
Priority date	Apr 27, 2018
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

Implementations of a method of forming semiconductor packages may include: providing a wafer having a plurality of devices, etching one or more trenches on a first side of the wafer between each of the plurality of devices, applying a molding compound to the first side of the wafer to fill the one or more trenches; grinding a second side of the wafer to a desired thickness, and exposing the molding compound included in the one or more trenches. The method may include etching the second side of the wafer to expose a height of the molding compound forming one or more steps extending from the wafer, applying a back metallization to a second side of the wafer, and singulating the wafer at the one or more steps to form a plurality of semiconductor packages. The one or more steps may extend from a base of the back metallization.

First claim

What is claimed is:

1. A wafer comprising:
a first side and a second side, the second side opposite the first side;
a plurality of devices; and
a plurality of trenches formed through the wafer;
wherein a metal layer is coupled to the second side of the wafer, the metal layer comprising a plurality of ridges; and
wherein a molding compound is coupled over the wafer and into a plurality of trenches formed within the metal layer.

2. The wafer of claim 1 , wherein the molding compound extends across an interface between the second side of the wafer and the metal layer.

3. The wafer of claim 1 , wherein a depth of each trench of the plurality of trenches formed within the metal layer is 3 to 10 microns.

4. The wafer of claim 1 , wherein a height of each ridge of the plurality of ridges is substantially the same as a depth of each trench of the plurality of trenches formed within the metal layer.

5. The wafer of claim 1 , wherein the plurality of ridges is aligned with the plurality of trenches formed through the wafer.

6. The wafer of claim 1 , wherein the metal layer comprises one of copper plating, nickel plating, gold plating, tin/silver plating, or any combination thereof.

7. A method of forming a wafer comprising:
providing a wafer comprising a plurality of devices;
forming one or more trenches in a first side of the wafer;
applying a molding compound to the first side of the wafer, wherein the molding compound fills the one or more trenches;
forming one or more steps between the molding compound and the wafer through thinning the second side of the wafer; and
applying a back metallization over the one or more steps between the molding compound and the wafer.

8. The method of claim 7 , further comprising grinding the first side of the wafer to expose one or more bumps comprised in the plurality of devices.

9. The method of claim 7 , wherein thinning the second side of the wafer comprises dry etching.

10. The method of claim 7 , wherein a width of the one or more trenches each comprise a width of 50 to 100 microns.

11. The method of claim 7 , wherein the one or more steps comprise a height of 3 to 10 microns.

12. The method of claim 7 , wherein the back metallization comprises sputtered Ti/Cu.

13. The method of claim 7 , wherein the back metallization comprises one of copper plating, nickel plating, gold plating, tin/silver plating, or any combination thereof.

14. A semiconductor package comprising:
a substrate having a first side and a second side, the second side opposite the first side;
a device coupled over the first side of the substrate;
a metal layer coupled to and covering an entirety of the second side of the substrate, the metal layer comprising a ridge formed along an outer perimeter of the semiconductor package; and
a molding compound coupled over the device and coupled into a notch within the metal layer.

15. The semiconductor package of claim 14 , wherein the molding compound covers an interface between the second side of the substrate and the metal layer.

16. The semiconductor package of claim 14 , wherein the ridge comprises a continuous ridge.

17. The semiconductor package of claim 14 , wherein a height of the ridge is substantially the same as a height of the notch.

18. The semiconductor package of claim 14 , wherein the molding compound covers a plurality of sidewalls of the substrate.

19. The semiconductor package of claim 14 , wherein the ridge is aligned with the notch.

20. The semiconductor package of claim 14 , wherein the metal layer comprises one of copper plating, nickel plating, gold plating, tin/silver plating, or any combination thereof.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Kurose Eiji

Classifications

• H10W74/127

  characterised by arrangements for sealing or adhesion · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/983

  Reinforcing structures, e.g. collars · CPC title

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/501

  for use before dicing · CPC title