Dummy cell arrangement and method of arranging dummy cells

Patent metadata

Field	Value
Publication number	US-10153265-B1
Application number	US-201715681439-A
Country	US
Kind code	B1
Filing date	Aug 21, 2017
Priority date	Aug 21, 2017
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.

First claim

What is claimed is:

1. A dummy cell arrangement in a semiconductor device, comprising:
a substrate with a dummy region;
a plurality of unit dummy cells arranged in rows and columns in said dummy region, wherein each unit dummy cell comprises exactly one base dummy unit and exactly two fixed dummy units at two opposite sides of said exactly one base dummy unit in a row direction or in a column direction, and said base dummy unit comprises at least one fin, at least one gate traversing said at least one fin and at least one contact on said at least one fin;
a plurality of standard extended dummy cells arranged at the end of said unit dummy cells in rows and columns, wherein each said standard extended unit dummy cell comprises at least two said base dummy units and exactly two fixed dummy units at two opposite sides of said at least two base dummy units in the row direction or in the column direction, said exactly two base dummy units are directly contacting one another, and said fixed dummy unit is larger than said base dummy unit; and
a plurality of flexible extended dummy cells arranged at the end of said unit dummy cells in rows and columns and filling up remaining said dummy region, wherein each flexible extended dummy cell comprises at least two said base dummy units and a plurality of flexible dummy units arranged at two opposite sides of said at least two base dummy units in the row direction or in the column direction, and said flexible dummy unit comprises one said gate and one said contact, wherein said at least one gate in said base dummy unit and said gate in said flexible dummy units are a plurality gates, and each of said gates is a singular gate being vertically arranged.

2. The dummy cell arrangement in a semiconductor device according to claim 1 , wherein said base dummy unit is a dummy unit having a minimum pitch in said row direction or said column direction.

3. The dummy cell arrangement in a semiconductor device according to claim 1 , wherein said fixed dummy unit comprises at least one said fin, at least one said gate traversing said at least one fin and at least one said contact on said at least one fin, and said fixed dummy unit is larger than said base dummy unit.

4. A dummy cell arrangement in a semiconductor device, comprising:
a substrate with a dummy region, wherein said dummy region is filled with a plurality of unit dummy cells, a plurality of standard extended dummy cells and a plurality of flexible extended dummy cells, each of said flexible extended dummy cells is disposed directly contacting one of said unit dummy cells or one of said standard extended dummy cells, each of said standard extended dummy cells is disposed directly contacting one of said unit dummy cells, wherein each of said unit dummy cells includes exactly one base dummy unit and exactly two fixed dummy units at two opposite sides of said exactly one base dummy unit in a row direction or in a column direction, and said base dummy unit includes one gate, at least one fin, and one contact, wherein said gate is perpendicularly arranged with respect to said at least one fin, and said contact is disposed on said at least one fin, and said fixed dummy unit includes said at least one fin, a plurality of said gates and a plurality of said contacts, wherein said gates are perpendicularly arranged with respect to said at least one fin, and said contacts are disposed on said at least one fin, and said fixed dummy unit is larger than said base dummy unit, and said each standard extended dummy cell includes at least two said base dummy units and at least two said fixed dummy units, and said each flexible extended dummy cell includes at least two said base dummy units, said fixed dummy unit and one flexible cell, wherein said flexible cell includes a plurality of flexible dummy units, and each flexible dummy unit includes one said gate and one said contact, wherein adjacent said flexible dummy units are in direct contact with each other; and at least one of said flexible dummy units is in direct contact with one of said at least two base dummy unit of said each flexible extended dummy cell.

Assignees

• United Microelectronics Corp

Inventors

• Chu Chung-Liang
• Chen Yu-Ruei
• Lin Yu-Hsiang

Classifications

• H01L27/0207 Primary

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L21/823475

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic

• H10D84/834

  comprising FinFETs · CPC title