Method for forming a structure with a hole

US12040229B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12040229-B2
Application numberUS-202217989875-A
CountryUS
Kind codeB2
Filing dateNov 18, 2022
Priority dateAug 22, 2019
Publication dateJul 16, 2024
Grant dateJul 16, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for forming a structure with a hole on a substrate is disclosed. The method may comprise: depositing a first structure on the substrate; etching a first part of the hole in the first structure; depositing a plug fill in the first part of the hole; depositing a second structure on top of the first structure; etching a second part of the hole substantially aligned with the first part of the hole in the second structure; and, etching the plug fill of the first part of the hole and thereby opening up the hole by dry etching. In this way 3-D NAND device may be provided.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of forming a structure with a hole on a substrate, the method comprising: providing a substrate having a structure with a hole formed therein; depositing a plug fill in a first part of the hole; depositing a second structure on top of the first structure; etching a second part of the hole substantially aligned with the first part of the hole in the second structure; and, etching the plug fill of the first part of the hole and thereby opening up the hole, wherein etching the plug fill comprises dry etching, wherein depositing the plug fill comprises deposition steps with at least one etch step. 2. The method of claim 1 , wherein etching the plug fill comprises providing the substrate to a reaction chamber constructed and arranged to provide a gaseous etchant for isotropic etching the plug fill in the reaction chamber. 3. The method of claim 2 , wherein etching the plug fill comprises providing one or more of the gaseous etchants comprising a halide to the reaction chamber. 4. The method of claim 3 , wherein the halide is selected from the group consisting of nitrogen trifluoride (NF 3 ) and chlorine (Cl 2 ) for thermally activated etching the plug. 5. The method of claim 2 , wherein during etching the plug fill the temperature in the reaction chamber is below 500° C. and the pressure in the reactor is below 1 Torr and the reaction chamber is substantially radical and/or ion free. 6. The method of claim 3 , wherein the halide is selected from boron chloride (BCl 3 ); fluorine (F 2 ), fluoroform (CHF 3 ), sulfur hexafluoride (SF 6 ), tetrafluoromethane (CF 4 ) in the reaction chamber for dry etching the plug. 7. The method according to claim 1 , wherein the method comprises loading the substrate to a boat and moving the boat with substrates to a batch reactor of a vertical furnace for processing. 8. The method according to claim 1 , wherein depositing the plug fill comprises providing a germanium precursor. 9. The method according to claim 8 wherein the germanium precursor comprise a precursor selected from the group consisting of germane, digermane, dichlorogermane, trichlorogermane, tetrachlorogermane, germanium alkoxide, and any combination thereof. 10. The method according to claim 8 , wherein depositing the plug fill comprises providing a silicon precursor and the plug fill comprises silicon germanium (SiGe) with a germanium content from 1% to 100%. 11. The method according to claim 10 , wherein the silicon precursor comprising a precursor selected from the group consisting of silane, disilane, trisilane, chlorosilane, dichlorosilane, trichlorosilane, tetrachlorosilane, methylsilane, dimethylsilane, trimethylsilane, tetramethylsilane, and any combination thereof. 12. A method of forming a structure with a hole on a substrate, the method comprising: depositing a first structure on the substrate; etching a first part of the hole in the first structure; depositing a plug fill in the first part of the hole; depositing a second structure on top of the first structure; etching a second part of the hole substantially aligned with the first part of the hole in the second structure; and, etching the plug fill of the first part of the hole and thereby opening up the hole, wherein etching the plug fill comprises dry etching, wherein depositing the plug fill comprises providing a germanium precursor, wherein depositing the plug fill comprises providing a silicon precursor and the plug fill comprises silicon germanium (SiGe) with a germanium content from 1% to 100%, and wherein a ratio of germanium to silicon is modulated during depositing the silicon germanium to manipulate the germanium content in the silicon germanium from a first layer of the plug towards the center and top of the plug. 13. The method according to claim 12 , wherein depositing the plug fill comprises deposition steps with at least one etch step. 14. A method of forming a structure with a hole on a substrate, the method comprising: depositing a first structure on the substrate; etching a first part of the hole in the first structure; depositing a plug fill in the first part of the hole; depositing a second structure on top of the first structure; etching a second part of the hole substantially aligned with the first part of the hole in the second structure; etching the plug fill of the first part of the hole and thereby opening up the hole, wherein etching the plug fill comprises dry etching, and depositing a seed layer on top of the first structure and in the first part of the hole before depositing a plug fill in the first part of the hole. 15. The method according to claim 14 , wherein the seed layer comprises silicon, silicon oxide and/or germanium oxide. 16. The method according to claim 14 , wherein depositing the seed layer comprises providing a germanium precursor and the germanium precursor is selected from germane, digermane, dichlorogermane, trichlorogermane, tetrachlorogermane, germanium alkoxide, or a combination thereof. 17. The method according to claim 14 , wherein depositing the seed layer comprises providing a silicon precursor wherein the silicon precursor comprises silane, disilane, trisilane, chlorosilane, dichlorosilane, trichlorosilane, tetrachlorosilane, methylsilane, dimethylsilane, trimethylsilane, tetramethylsilane, or any combination thereof. 18. The method according to claim 14 , wherein depositing the seed layer comprises depositing the seed layer with a thickness smaller than 10 nanometer. 19. The method according to claim 14 wherein the method comprises removing the seed layer with a dry etch. 20. The method of claim 19 , wherein the method comprises providing the substrate to a reaction chamber constructed and arranged to provide a gaseous etchant for isotropic etching the seed layer. 21. The method of claim 20 , wherein the method comprises providing one or more of the gaseous etchants comprising a halide to the reaction chamber. 22. The method of claim 21 wherein the halide is selected from nitrogen trifluoride NF 3 and chlorine Cl 2 , in the reaction chamber for dry etching the plug. 23. The method of claim 21 , wherein the temperature in the reaction chamber is below 500° C. and the pressure in the reaction chamber is below 1 Torr and the reaction chamber is substantially radical and/or ion free. 24. The method of claim 1 , wherein etching the second part of the hole comprises anisotropic etching. 25. The method of claim 1 , wherein the method comprises polishing the plug fill before depositing the second structure on top of the first structure. 26. The method of claim 1 , wherein any of the above steps are repeated to form a 3-D NAND device. 27. The method of claim 1 , wherein depositing the second structure on the substrate comprising depositing a bilayer structure on the substrate, the bilayer structure comprising alternating layers of a silicon oxide layer and a silicon nitride layer. 28. The method according to claim 1 , wherein the opening of the hole in the structure has a width smaller than 200 nm.

Assignees

Inventors

Classifications

  • Through-vias · CPC title

  • for connecting multiple chips together · CPC title

  • H10W20/081Primary

    by forming openings in the dielectric parts · CPC title

  • H10W20/057Primary

    by selectively depositing, e.g. by using selective CVD or plating · CPC title

  • H10P50/283Primary

    by chemical means · CPC title

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What does patent US12040229B2 cover?
A method for forming a structure with a hole on a substrate is disclosed. The method may comprise: depositing a first structure on the substrate; etching a first part of the hole in the first structure; depositing a plug fill in the first part of the hole; depositing a second structure on top of the first structure; etching a second part of the hole substantially aligned with the first part of …
Who is the assignee on this patent?
Asm Ip Holding Bv
What technology area does this patent fall under?
Primary CPC classification H10W20/081. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 16 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).