Multi-pressure bipolar electrostatic chucking

US12040210B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12040210-B2
Application numberUS-202017073671-A
CountryUS
Kind codeB2
Filing dateOct 19, 2020
Priority dateOct 19, 2020
Publication dateJul 16, 2024
Grant dateJul 16, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Exemplary semiconductor processing systems include a processing chamber, a power supply, and a chuck disposed at least partially within the processing chamber. The chuck includes a chuck body defining a vacuum port. The chuck also includes first and second coplanar electrodes embedded in the chuck body and connected to the power supply. In some examples, coplanar electrodes include concentric electrodes defining a concentric gap in between. Exemplary semiconductor processing methods may include activating the power supply for the electrostatic chuck to secure a semiconductor substrate on the body of the chuck and/or activating the vacuum port defined by the body of the electrostatic chuck. Some processing can be carried out at increased pressure, while other processing can be carried out at reduced pressure with increased chucking voltage.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor processing system comprising: a processing chamber; a power supply; and an electrostatic chuck disposed at least partially within the processing chamber, the electrostatic chuck further comprising: a chuck body defining a vacuum port; and first and second coplanar electrodes embedded in the chuck body and connected to the power supply, wherein the vacuum port extends from a bottom surface of the chuck body through the second coplanar electrode to a top surface of the chuck body. 2. The semiconductor processing system of claim 1 , wherein the first and second coplanar electrodes comprise semicircular mesh electrodes defining a linear gap in between. 3. The semiconductor processing system of claim 1 , further comprising a ground terminal connected to the processing chamber. 4. The semiconductor processing system of claim 3 , wherein the power supply is configured to be floating relative to ground. 5. The semiconductor processing system of claim 1 , wherein the first and second coplanar electrodes comprise concentric electrodes defining a concentric gap in between, wherein the concentric electrodes and the concentric gap are coextensive with a majority of a circumference of the chuck body. 6. The semiconductor processing system of claim 5 , wherein each of the concentric electrodes comprises at least two concentric sections. 7. The semiconductor processing system of claim 5 , wherein the power supply is configured to selectively reverse a polarity of a chucking voltage to at least one of the concentric electrodes. 8. A method of processing a substrate in a semiconductor substrate, the method comprising: activating a power supply for an electrostatic chuck using at or near a maximum value for a voltage of the power supply to secure a semiconductor substrate on a body of the electrostatic chuck; activating a vacuum port defined by the body of the electrostatic chuck; reducing the voltage while increasing a pressure in an interior of a semiconductor processing chamber that includes the body of the electrostatic chuck and the semiconductor substrate; processing a semiconductor substrate disposed on the electrostatic chuck using sub-atmospheric chemical vapor deposition at increased pressure; reducing the pressure in the interior of the semiconductor processing chamber while increasing the voltage of the power supply; striking plasma in the interior of the semiconductor processing chamber at reduced pressure; and performing plasma-enhanced processing of the semiconductor substrate. 9. The method of claim 8 further comprising operating a plurality of lift pins to reduce a spacing between the body of the electrostatic chuck and the semiconductor substrate for at least one of the selective-area chemical vapor deposition or the plasma-enhanced processing. 10. The method of claim 8 , wherein the increased pressure is about 500 Torr and the reduced pressure is about 7 Torr. 11. The method of claim 8 further comprising reversing a polarity of the voltage applied to one of a pair of electrodes in the body of the electrostatic chuck prior to the plasma-enhanced processing. 12. The method of claim 11 , wherein reversing the polarity further comprises ramping the voltage applied to the one of the pair of electrodes down prior to reversing the polarity and up after reversing the polarity, at a rate sufficient to avoid popping the semiconductor substrate. 13. The method of claim 12 , wherein the one of the pair of electrodes comprises a concentric section closest to an outer edge of the body of the electrostatic chuck. 14. The method of claim 8 further comprising replacing gas in the interior of the semiconductor processing chamber with an inert gas having a breakdown voltage higher than the maximum value for the voltage of the power supply when transitioning between pressures. 15. The method of claim 14 wherein the inert gas comprises nitrogen. 16. An electrostatic chuck comprising: a chuck body defining a vacuum port, wherein the vacuum port extends from a bottom surface of the chuck body to a top surface of the chuck body; and first and second coplanar, concentric electrodes embedded in the chuck body configured to be connected to a power supply, the first and second coplanar, concentric electrodes defining a concentric gap in between, the first concentric electrode comprising first and second concentric sections, and the second concentric electrode comprising first and second concentric sections, wherein: the first concentric section of the first electrode substantially surrounds the first concentric section of the second electrode; the second concentric section of the second electrode substantially surrounds the first concentric section of the first electrode; and the second concentric section of the first electrode substantially surrounds the second concentric section of the second electrode, wherein the vacuum port extends through the first concentric section of the second electrode. 17. The electrostatic chuck of claim 16 wherein the first and second coplanar, concentric electrodes and the concentric gap are coextensive with a majority of a circumference of the chuck body. 18. The electrostatic chuck of claim 17 , wherein each of the first and second coplanar, concentric electrodes comprises at least two concentric sections. 19. The electrostatic chuck of claim 16 , wherein the power supply is configured to selectively reverse a polarity of a chucking voltage to at least one of the first and second coplanar, concentric electrodes. 20. The electrostatic chuck of claim 19 , wherein the first and second coplanar, concentric electrodes are configured so that a concentric section closest to an outer edge of the chuck body is operable to selectively reverse the polarity.

Assignees

Inventors

Classifications

  • characterised by lifting arrangements, e.g. lift pins · CPC title

  • H10P72/722Primary

    Details of electrostatic chucks · CPC title

  • using vacuum or suction, e.g. Bernoulli chucks · CPC title

  • using electric discharges {(generation and control of plasma in discharge tubes for surface treatment H01J37/32, H01J37/34)} · CPC title

  • Holding mechanisms · CPC title

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What does patent US12040210B2 cover?
Exemplary semiconductor processing systems include a processing chamber, a power supply, and a chuck disposed at least partially within the processing chamber. The chuck includes a chuck body defining a vacuum port. The chuck also includes first and second coplanar electrodes embedded in the chuck body and connected to the power supply. In some examples, coplanar electrodes include concentric e…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10P72/722. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 16 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).