Method for manufacturing semiconductor structure with resistive elements

Patent metadata

Field	Value
Publication number	US-12040178-B2
Application number	US-202318307197-A
Country	US
Kind code	B2
Filing date	Apr 26, 2023
Priority date	Nov 9, 2017
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

A semiconductor device structure and method for manufacturing the same are provided. The method includes forming a first resistive element over a substrate, and the first resistive element has a first sidewall extending in a first direction and a second sidewall opposite to the first sidewall and extending in the first direction. The method further includes forming a first conductive feature and a second conductive feature over and electrically connected to the first resistive element and forming a second resistive element over the first resistive element and spaced apart from the first resistive element in a second direction. In addition, the second resistive element is located between the first sidewall and the second sidewall of the first resistive element in a top view, and the first resistive element and the second resistive element are made of different nitrogen-containing materials.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
forming a first resistive element over a substrate, wherein the first resistive element has a first sidewall extending in a first direction and a second sidewall opposite to the first sidewall and extending in the first direction;
forming a first conductive feature and a second conductive feature over and electrically connected to the first resistive element; and
forming a second resistive element over the first resistive element and spaced apart from the first resistive element in a second direction, wherein the second resistive element is located between the first sidewall and the second sidewall of the first resistive element in a top view, and the first resistive element and the second resistive element are made of different nitrogen-containing materials,
wherein the first conductive feature is sandwiched between the first resistive element and the second resistive element in the second direction.

2. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein the first conductive feature and the second conductive feature are located between the first sidewall and the second sidewall of the first resistive element in the top view.

3. The method for manufacturing a semiconductor structure as claimed in claim 1 , further comprising:
forming a third resistive element over the second conductive feature, wherein the second resistive element and the third resistive element are made a same nitrogen-containing material.

4. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein the first resistive element has a first dimension in the second direction, the second resistive element has a second dimension in the second direction, and the first dimension is greater than the second dimension.

5. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein the first conductive feature and the second conductive feature are formed after forming the second resistive element.

6. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein the second resistive element has a second dimension in the second direction, the first conductive feature has a third dimension in the second direction, and the third dimension is greater than the second dimension.

7. The method for manufacturing a semiconductor structure as claimed in claim 1 , further comprising:
forming a dielectric layer over the first resistive element before forming the second resistive element, wherein the first conductive feature penetrates into the dielectric layer and lands on a top surface of the first resistive element.

8. The method for manufacturing a semiconductor structure as claimed in claim 7 , wherein a bottom surface of the second resistive element is in contact with a top surface of the dielectric layer.

9. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein a bottom surface of the first conductive feature is higher than a bottom surface of the first resistive element and is lower than a top surface of the first resistive element.

10. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein the first conductive feature continuously extends from a bottom surface of the second resistive element to a top surface of the first resistive element in the second direction.

11. A method for manufacturing a semiconductor structure, comprising:
forming a first resistive material over a substrate;
patterning the first resistive material to form a first resistive element;
forming a dielectric layer around the first resistive element;
forming a first conductive feature and a second conductive feature through the dielectric layer and in contact with a top surface of the first resistive element after forming the first resistive element;
forming a second resistive material over the dielectric; and
patterning the second resistive material to form a second resistive element, wherein the second resistive element is vertically spaced apart from the first resistive element.

12. The method for manufacturing a semiconductor structure as claimed in claim 11 , wherein the first resistive element has a first projection area in a top view, the second resistive element has a second projection area in the top view, and the first projection area is greater than the second projection area.

13. The method for manufacturing a semiconductor structure as claimed in claim 12 , wherein the second projection area is fully inside the first projection area in the top view.

14. The method for manufacturing a semiconductor structure as claimed in claim 12 , wherein the first conductive feature has a third projection area in the top view, and the third projection area is fully inside the second projection area.

15. The method for manufacturing a semiconductor structure as claimed in claim 11 , wherein the first conductive feature partially extends into the first resistive element.

16. The method for manufacturing a semiconductor structure as claimed in claim 11 , wherein the first resistive element is formed after forming the first conductive feature and the second conductive feature.

17. A method for manufacturing a semiconductor structure, comprising: forming a first resistive material over a top surface of a first dielectric layer, wherein the first resistive material has a first atomic concentration of nitrogen; patterning the first resistive material to form a first resistive element; forming a second dielectric layer around and covering the first resistive element; patterning the second dielectric layer to expose a first portion of the top surface of the first dielectric layer while the first resist element is covered by the second dielectric layer; forming a second resistive material over the second dielectric layer and the first portion of the top surface of the first dielectric layer, wherein the second resistive material has a second atomic concentration of nitrogen, and the second atomic concentration of nitrogen is greater than the first atomic concentration of nitrogen; and partially removing the second resistive material to form a second resistive element, wherein the second resistive element is spaced apart from the first resistive element by the second dielectric layer.

18. The method for manufacturing a semiconductor structure as claimed in claim 17 , wherein a top surface of the first resistive element is substantially level with a top surface of the second resistive element.

19. The method for manufacturing a semiconductor structure as claimed in claim 17 , further comprising:
forming a first conductive structure over the first resistive element, wherein a bottom portion of the first conductive structure extends into the first resistive element.

20. The method for manufacturing a semiconductor structure as claimed in claim 18 , wherein a bottom surface of the first resistive element is substantially level with a bottom surface of the second resistive element.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsueh Hsiu-Wen
• Chen Yu-Hsiang
• Huang Wen-Sheh
• Chen Chii-Ping
• Chen Wan-Te

Classifications

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W40/10

  Arrangements for heating · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title