System and method for measuring intermittent operating life of GaN-based device

Patent metadata

Field	Value
Publication number	US-12038469-B2
Application number	US-202117419309-A
Country	US
Kind code	B2
Filing date	Feb 26, 2021
Priority date	Feb 26, 2021
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

The present invention provides a system and method for measuring an intermittent operating life (IOL) of a GaN-based device under test (DUT) is provided. The system is operable in a stressing mode, a cooling mode and a measure mode. A power regulation approach is adopted to ensure that DUT of the same thermal resistance have same temperature increase during the IOL test. The present invention eliminates the influence caused by parasitic parameters of testing circuits and the inconsistency of threshold voltage and drain-source resistance of the device itself. Through power regulation, it is the junction temperature of the device, not the housing temperature of the device, being directly controlled. Therefore, higher measurement accuracy can be achieved.

First claim

The invention claimed is:

1. A system for measuring an intermittent operating life (IOL) of a GaN-based device under test (DUT), the system being operable in a stressing mode, a cooling mode, and a measure mode, the system being operable in the stressing mode, the measure mode, the cooling mode, and the measure mode in sequence, and comprising:
a controlling circuit configured for detecting a signal V D_IM from a drain terminal of the DUT and a signal V S_IM from a source terminal of the DUT and computing a drain-source resistance R ds of the DUT when the system is operated in the measure mode;
a stressing circuit configured for applying a regulated stressing power P str to the DUT to increase a junction temperature of the DUT to an ON-junction temperature T jON when the system is operated in the stressing mode, wherein the regulated stressing power P str is given by P str =I ds_str *V ds_str , where I ds_str is a regulated drain-source current passing through the DUT and V ds_str is a regulated drain-source voltage V ds_str across the DUT;
a cooling circuit configured for, after the DUT is turned off, cooling the DUT to decrease the junction temperature of the DUT to an OFF junction temperature T jOFF ;
a gate-bias circuit configured to receive a control signal VG_M from the controlling circuit to turn on the DUT when the system is operated in the measure mode; and receive a control signal VG_OFF from the controlling circuit to turn off the DUT when the system is operated in the cooling mode; and
a measure-bias circuit configured to receive, after the DUT is turned on, a reference signal IM_Ctrl from the controlling circuit and supply a regulated drain-source current I ds_mea to the DUT when the system is operated in the measure mode, such that the controlling circuit computes the drain-source resistance R ds of the DUT;
wherein the controlling circuit is further configured to
determine the drain-source resistance R ds to be an ON-drain-source resistance R ds_ON of the DUT if the drain-source resistance R ds is obtained when the junction temperature of the DUT reaches the ON-junction temperature T jON ; and
determine the drain-source resistance R ds to be an OFF-drain-source resistance R ds_OFF of the DUT if the drain-source resistance R ds is obtained when the junction temperature of the DUT reaches the OFF junction temperature T jOFF ;
wherein the gate-bias circuit comprises a gate-bias power supply PS_VG and a first switching device M 1 connected to the gate-bias power supply PS_VG; an end of the first switching device M 1 is connected to the gate-bias power supply PS_VG, and another end of the first switching device M 1 is connected to a VG node; the VG node is connected to a gate of the DUT; the controlling circuit is configured to control the first switching device M 1 to connect the gate-bias power supply PS_VG to the VG node to turn on the DUT when the system is operated in the measure mode;
wherein the gate-bias circuit further comprises a third switching device M 3 ; an end of the third switching device M 3 is connected to a ground GND, and another end of the third switching device M 3 is connected to the VG node; the third switching device M 3 is configured to receive a control signal VG_OFF from the controlling circuit to connect the ground GND to the VG node to turn off the DUT.

2. The system according to claim 1 , wherein the T jON is given by T jON =P str ×R th(j-a) +T a , where T a is an ambient temperature and R th(j-a) is a junction thermal resistance of the DUT at the ambient temperature T a .

3. The system according to claim 1 , wherein the OFF junction temperature T jOFF is given by T jOFF =T a , where T a is an ambient temperature.

4. The system according to claim 1 , wherein the stressing circuit is further configured to:
receive a first reference signal V ds_Ctrl and a second reference signal I ds_Ctrl from the controlling circuit;
detect the signal V D_IM from the drain terminal of the DUT and the signal V S_IM from the source terminal of the DUT;
control a voltage applied to the drain terminal of the DUT based on the received first reference signals V ds_Ctrl and the detected signal V D_IM to regulate the drain-source voltage V ds_str to be equal to V ds_Ctrl ; and
control a voltage applied to the VG node based on the received second reference signals I ds_Ctrl and the detected signal V S_IM to regulate the drain-source current I ds_str to be equal to

I

ds
⁢
_
⁢
Ctrl

R
⁢
1

.

5. The system according to claim 1 , further comprising a fourth diode D 4 having a cathode coupled to the drain terminal of the DUT, and configured for allowing the drain-source current I ds_str flowing only in one direction from the stressing circuit to the drain terminal of the DUT.

6. The system according to claim 5 , further comprising a fourth switching device M 4 having a drain terminal connected to the stressing circuit, a source terminal connected to an anode of the fourth diode D 4 , and a gate terminal connected to the controlling circuit.

7. The system according to claim 6 , wherein the controlling circuit is further configured to
turn on the fourth switching device M 4 to conduct the drain-source current I ds_str flowing from the stressing circuit to the drain terminal of the DUT when the system is operated in the stressing mode; and
turn off the fourth switching device M 4 to block the drain-source current I ds_str flowing from the stressing circuit to the drain terminal of the DUT when the system is not operated in the stressing mode.

8. The system according to claim 1 , further comprising a fifth diode D 5 having a cathode connected to the drain terminal of the DUT and configured for allowing the drain-source current I ds_mea flowing only in one direction from the measure-bias circuit to the drain terminal of the DUT.

9. The system according to claim 8 , further comprising a sixth switching device M 6 having a drain terminal connected to the measure-bias circuit, a source terminal connected to an anode of the fifth diode D 5 , and a gate terminal connected to the controlling circuit for receiving a control signal S/M.

10. The system according to claim 8 , wherein the controlling circuit is configured to turn on the sixth switching device M 6 to conduct the drain-source current I ds_mea flowing from the measure-bias circuit to the drain terminal of the DUT when the testing system is operated in the measure mode; and turn off the sixth switching device M 6 to block the drain-source current I ds_mea flowing from the measure-bias circuit to the drain terminal of the DUT when the system is not operated in the measure mode.

11. The system according to claim 1 , wherein the cooling circuit comprises a fan configured to receive a control signal Air_Ctrl from the controlling circuit and generate a flow of air surrounding the DUT to cool down the DUT.

12. The system according to claim 1 , further comprising a man-machine interfacing unit configured for facilitating a user to select and set up operation modes and displaying operation setting menus and measurement results.

13. The system according to claim 1 , further comprising a storage unit configured for storing oper

Assignees

• Innoscience Suzhou Technology Holding Co Ltd

Inventors

• Chen Chang
• Zhou Chunhua
• Li sichao
• Yang Rong
• Bai Donghua
• Huang Jiabiao

Classifications

• G01R31/2619

  for measuring thermal properties thereof · CPC title

• G01R31/2617

  for measuring switching properties thereof · CPC title

• G01R31/2621

  for testing field effect transistors, i.e. FET's · CPC title

• G01R31/2642 Primary

  Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests · CPC title

• G01R31/2628 Primary

  for measuring thermal properties thereof · CPC title