Apparatus and method for Sigma-Delta modulator quantization noise cancellation

Patent metadata

Field	Value
Publication number	US-12034460-B2
Application number	US-202217869173-A
Country	US
Kind code	B2
Filing date	Jul 20, 2022
Priority date	Jul 20, 2022
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

Described herein is a fractional phase locked loop with sigma-delta modulator (SDM) quantization noise cancellation. The fractional phase includes a digital filter configured to receive an error signal based on a comparison of a reference clock and a feedback clock, a controlled oscillator configured to generate an output clock by adjusting a frequency of the controlled oscillator based on a control signal output by the digital filter, the feedback clock being based on the output clock, a sigma-delta modulator configured to control division of the output clock to generate a divided output clock which includes a sigma-delta modulator quantization noise and a digital-to-time converter configured to receive a cancellation code from an integrator in the sigma-delta modulator and cancel the sigma-delta modulator quantization noise in the divided output clock with the cancellation code to generate the feedback clock.

First claim

What is claimed is:

1. A fractional phase locked loop comprising:
a digital filter configured to receive an error signal based on a comparison of a reference clock and a feedback clock;
a controlled oscillator configured to generate an output clock by adjusting a frequency of the controlled oscillator based on a control signal output by the digital filter, the feedback clock being based on the output clock;
a sigma-delta modulator configured to control division of the output clock to generate a divided output clock which includes a sigma-delta modulator quantization noise; and
a digital-to-time converter configured to
receive a cancellation code from an integrator in the sigma-delta modulator; and
cancel the sigma-delta modulator quantization noise in the divided output clock with the cancellation code to generate the feedback clock, and

the digital-to-time converter comprising
a cancellation circuit configured to phase align and cancel the sigma-delta modulator quantization noise with the cancellation code to generate an output, the cancellation circuit having a convergence point based on setting a resistor-capacitor constant to a controlled oscillator target period and implementing to a defined voltage; and
a cancellation point adjustment circuit configured to compensate for voltage based changes in the convergence point by comparing the output of the cancellation circuit with a reference voltage which tracks the voltage based changes,
wherein the voltage based changes are tracked using a least means square algorithm which uses a statistical output from the digital filter.

2. The fractional phase locked loop of claim 1 , the digital-to-time converter comprising a capacitor array digitally controlled by the cancellation code to achieve a desired phase delay of the cancellation code to substantially match a phase of the sigma-delta modulator quantization noise.

3. The fractional phase locked loop of claim 2 , wherein a cancellation point is determined by setting a resistor-full scale capacitor array constant to a target period of the controlled oscillator and implementing to a defined voltage.

4. The fractional phase locked loop of claim 1 , the digital-to-time converter comprising a reset circuit configured to reset the digital-to-time converter to a zero voltage value for each cancellation code.

5. The fractional phase locked loop of claim 1 , wherein the digital-to-time converter uses one edge of the divided output clock to reset the digital-to-time converter to remove memory effects for each cancellation code and uses another edge of the divided output clock to substantially phase align the sigma-delta modulator quantization noise and the cancellation code.

6. A digital-to-time converter comprising:
a first circuit configured to receive a cancellation code; and
a second circuit configured to receive a clock embedded with a quantization noise due to a sigma-delta modulator,
wherein the first circuit and the second circuit are collectively configured to phase align and cancel the sigma-delta modulator quantization noise with the cancellation code to generate an output clock, and
wherein the digital-to-time converter has a cancellation point based on setting a resistor-capacitor constant of the digital-to-time converter to a controlled oscillator target period and implementing to a defined voltage,
wherein the first circuit and the second circuit use one edge of the clock to reset the digital-to-time converter to remove memory effects for each cancellation code and use another edge of the clock to substantially phase align the quantization noise with the cancellation code.

7. The digital-to-time converter of claim 6 , wherein the cancellation code is received from an internal integrator of the sigma-delta modulator.

8. The digital-to-time converter of claim 6 , wherein the first circuit includes a capacitor array digitally controlled by the cancellation code to obtain a desired phase delay for substantially matching the quantization noise.

9. The digital-to-time converter of claim 6 , further comprising a third circuit configured to compensate for voltage based changes in the cancellation point by comparing the output clock from the first circuit and the second circuit with a reference voltage which tracks the voltage based changes.

10. The digital-to-time converter of claim 9 , wherein the voltage based changes are tracked using a least means square algorithm which uses a statistical output from a digital filter in a phase locked loop.

11. The digital-to-time converter of claim 6 , further comprising a reset circuit configured to reset the digital-to-time converter to a zero voltage value for each cancellation code.

12. A method for improved quantization noise cancellation, the method comprising:
receiving, at a digital-to-time converter, a cancellation code from a sigma-delta modulator;
receiving, at the digital-to-time converter, a clock embedded with a quantization noise due to the sigma-delta modulator;
phase aligning, by the digital-to-time converter, the cancellation code with the quantization noise using a capacitor array controlled by the cancellation code; and
cancelling, by the digital-to-time converter, the quantization noise from the clock,
wherein the digital-to-time converter has a cancellation point based on setting a resistor-capacitor array constant of the digital-to-time converter to a controlled oscillator target period and implementing to a defined voltage, and
wherein voltage based changes in the cancellation point are tracked using a least means square algorithm which uses a statistical output from a digital filter in a phase locked loop.

13. The method of claim 12 , wherein the cancellation code is received from an internal integrator of the sigma-delta modulator.

14. The method of claim 12 , further comprising
compensating for the voltage based changes in the cancellation point by comparing a quantization noise cancelled clock with a reference voltage which tracks the voltage based changes.

15. The method of claim 12 , further comprising
resetting the digital-to-time converter to a zero voltage value for each cancellation code.

16. The method of claim 12 , further comprising
using one edge of the clock to reset the digital-to-time converter to remove memory effects for each cancellation code; and
using another edge of the clock to substantially phase align the quantization noise with the cancellation code.

Assignees

• Ciena Corp

Inventors

• Wen Tingjun
• Aouini Sadok
• Ben-Hamida Naim
• Mikkelsen Matthew
• Shalmani Soheyl Ziabakhsh
• Honarparvar Mohammad

Classifications

• H03M3/50 Primary

  Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004) · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title

• H03M3/43

  the quantiser being a single bit one · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title