Chip package, method of forming a chip package and method of forming an electrical contact
US-2017338169-A1 · Nov 23, 2017 · US
Chip package, method of forming a chip package and method of forming an electrical contact
US12033972B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12033972-B2 |
| Application number | US-202017090941-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 6, 2020 |
| Priority date | May 20, 2016 |
| Publication date | Jul 9, 2024 |
| Grant date | Jul 9, 2024 |
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- Title
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Abstract
Official abstract text for this publication.
A method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming an electrical contact, comprising: depositing, by atomic layer deposition, a non-conductive layer over at least a region of a metal surface; and after depositing, by atomic layer deposition, of the non-conductive layer over the at least a region of the metal surface, electrically contacting a region of the non-conductive layer with a metal contact structure, wherein the non-conductive layer comprises at least one material of a group of materials comprising aluminum oxide, aluminum nitride, silicon oxide, and/or silicon nitride materials; and wherein the metal contact structure comprises at least one metal of a group of metals comprising copper, silver, gold, palladium, and/or alloys thereof. 2. The method of claim 1 , wherein the region of the metal surface comprises copper. 3. The method of claim 1 , wherein the metal surface is a chip metallization. 4. The method of claim 1 , wherein a thickness of the non-conductive layer is in a range from about 1 nm to about 100 nm. 5. The method of claim 1 , wherein the metal contact structure is at least one metal of a group of metal contact structures comprising a wire, a coated wire, a bump, a micro-bump, a pillar, a clip, and/or a spring. 6. The method of claim 1 , wherein the metal surface is a surface of a leadframe. 7. The method of claim 1 , wherein the electrically contacting the metal surface with a metal contact structure comprises a bonding process. 8. The method of claim 7 , wherein the bonding process is a wedge bonding process. 9. A method of forming a chip package, the method comprising: forming an electrical contact, comprising: mounting a chip on a portion of a metal surface; depositing, by atomic layer deposition, a non-conductive layer over at least a region of a metal surface, wherein the non-conductive layer comprises at least one material of a group of materials comprising aluminum oxide, aluminum nitride, silicon oxide, and/or silicon nitride; and after depositing, by atomic layer deposition, the non-conductive layer over the at least a region of the metal surface, electrically contacting a region of the non-conductive layer with a metal contact structure, wherein the metal contact structure comprises at least one metal of a group of metals comprising copper, silver, gold, palladium, and/or alloys thereof. 10. The method of claim 9 , wherein the region of the metal surface comprises copper. 11. The method of claim 9 , further comprising: electrically contacting the chip with a second portion of the metal contact structure. 12. The method of claim 9 , further comprising: at least partially encapsulating the chip and the metal contact structure with a packaging material.
Assignees
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Classifications
Multilayered bond wires, e.g. having a coating concentric around a core · CPC title
comprising gold [Au] · CPC title
Forming coatings · CPC title
Encapsulations, e.g. protective coatings · CPC title
Die-attach connectors and bond wires · CPC title
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Frequently asked questions
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- What does patent US12033972B2 cover?
- A method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.
- Who is the assignee on this patent?
- Infineon Technologies Ag
- What technology area does this patent fall under?
- Primary CPC classification H10W70/465. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jul 09 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).