Method of operating nonvolatile memory device, nonvolatile memory device and memory controller performing the same

Patent metadata

Field	Value
Publication number	US-12033706-B2
Application number	US-202217873739-A
Country	US
Kind code	B2
Filing date	Jul 26, 2022
Priority date	Aug 12, 2021
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

First claim

What is claimed is:

1. A method of operating one or more nonvolatile memory devices, each nonvolatile memory device including one or more memory blocks, each memory block including a plurality of memory cells and a plurality of pages that are connected to a plurality of wordlines and arranged in a vertical direction, the method comprising:
setting pages arranged in a first direction of a channel hole as a first page to an N-th page, N being a natural number greater than or equal to two, the channel hole extending in the vertical direction, a size of the channel hole increasing in the first direction;
setting pages arranged in a second direction of the channel hole as an (N+1)-th page to a 2N-th page, the size of the channel hole decreasing in the second direction;
setting a first page pair to an N-th page pair such that a K-th page, among the first to the N-th pages, and an (N+K)-th page, among the (N+1)-th to the 2N-th pages, form one page pair, K being a natural number greater than or equal to one and less than or equal to N; and
driving the first to the N-th page pairs such that parity regions of two pages included in at least one page pair of the first to the N-th page pairs are shared by the two pages included in the at least one page pair.

2. The method of claim 1 , wherein:
the channel hole has a first portion to an N-th portion respectively corresponding to the first to the N-th pages and an (N+1)-th portion to an 2N-th portion respectively corresponding to the (N+1)-th to the 2N-th pages,
the first to the N-th portions of the channel hole have a first size to an N-th size, respectively,
the first size is a smallest size among the first to the N-th sizes, and the N-th size is a largest size among the first to the N-th sizes,
the (N+1)-th to the 2N-th portions of the channel hole have an (N+1)-th size to an 2N-th size, respectively, and
the (N+1)-th size is a largest size among the (N+1)-th to the 2N-th sizes, and the 2N-th size is a smallest size among the (N+1)-th to the 2N-th sizes.

3. The method of claim 2 , wherein:
the first to the N-th pages are included in a first memory block included in a first nonvolatile memory device, and are sequentially arranged along a first channel hole included in the first memory block, and
the (N+1)-th to the 2N-th pages are included in a second memory block included in a second nonvolatile memory device different from the first nonvolatile memory device, and are sequentially arranged along a second channel hole included in the second memory block.

4. The method of claim 2 , wherein:
the first to the N-th pages and the (N+1)-th to the 2N-th pages are included in a first memory block included in a first nonvolatile memory device, and are sequentially arranged along a first channel hole included in the first memory block, and
both the first page and the (N+1)-th page are provided at edge portions of the first memory block.

5. The method of claim 2 , wherein:
the first to the N-th pages and the (N+1)-th to the 2N-th pages are included in a first memory block included in a first nonvolatile memory device,
the first memory block includes a first channel hole, and the first channel hole includes a first sub-channel hole and a second sub-channel hole stacked in the vertical direction, and
the first to the N-th pages are sequentially arranged along the first sub-channel hole, and the (N+1)-th to the 2N-th pages are sequentially arranged along the second sub-channel hole.

6. The method of claim 5 , wherein:
the first memory block further includes an (2N+1)-th page to an (2N+J)-th page, J being a natural number greater than or equal to two,
the (2N+1)-th to the (2N+J)-th pages are sequentially arranged along the first sub-channel hole together with the first to the N-th pages,
the first sub-channel hole has an (2N+1)-th portion to an (2N+J)-th portion corresponding to the (2N+1)-th to (2N+J)-th pages, respectively, and the (2N+1)-th to the (2N+J)-th portions have an (2N+1)-th size to an (2N+J)-th size, respectively, and
the (2N+1)-th to the (2N+J)-th sizes are larger than the N-th size.

7. The method of claim 5 , wherein:
the first memory block includes a first sub-block and a second sub-block,
the first to the N-th pages are included in the first sub-block, and the (N+1)-th to the 2N-th pages are included in the second sub-block, and
the first sub-block and the second sub-block are independently programmed and erased.

8. The method of claim 2 , wherein:
the first to the N-th pages and the (N+1)-th to the 2N-th pages are included in a first memory block, the first memory block being included in a first nonvolatile memory device,
the first memory block includes a first channel hole, and the first channel hole includes a first sub-channel hole and a second sub-channel hole stacked in the vertical direction,
the first page to an M-th page, among the first to the N-th pages, and the (N+1)-th page to an (N+M)-th page, among the (N+1)-th to the 2N-th pages, are sequentially arranged along the first sub-channel hole, M being a natural number greater than or equal to two and less than N, and
an (M+1)-th page to the N-th page, among the first to the N-th pages, and an (N+M+1)-th page to the 2N-th page, among the (N+1)-th to the 2N-th pages, are sequentially arranged along the second sub-channel hole.

9. The method of claim 2 , wherein:
the first to the N-th pages are included in a first memory block, and the (N+1)-th to the 2N-th pages are included in a second memory block different from the first memory block,
the first memory block includes a first channel hole, and the first channel hole includes a first sub-channel hole and a second sub-channel hole stacked in the vertical direction,
the second memory block includes a second channel hole, and the second channel hole includes a third sub-channel hole and a fourth sub-channel hole stacked in the vertical direction, and
the first to the N-th pages are sequentially arranged along the first sub-channel hole, and the (N+1)-th to the 2N-th pages are sequentially arranged along the fourth sub-channel hole.

10. The method of claim 1 , wherein:
the first to the N-th pages and the (N+1)-th to the 2N-th pages are included in a first memory block, the first memory block being included in a first nonvolatile memory device, and are sequentially arranged along a first channel hole included in the first memory block, and
the first page is provided at an edge portion of the first memory block, and the (N+1)-th page is disposed at a center portion of the first memory block.

11. The method of claim 1 , wherein the driving the first to the N-th page pairs includes:
performing a data write operation on the first page pair including the first page and the (N+1)-th page.

12. The method of claim 11 , wherein the performing the data write operation on the first page pair includes:
receiving first data to be stored in the first page, second data to be stored in the (N+1)-th page, first parity data associated with the first data, and second parity data associated with the second data;
storing the first data and a portion of the first parity data in the first page; and
storing the second data, the second parity data, and a remaining portion of the first parity data in the (N+1)-th page.

13. The method of claim 12 , wherein the driving the first to the N-th page pairs further includes:
performing a data write operation on an X-th page pair including an X-th page and an (N+X)-th page, X being a natural number greater than or equal to two and less than or equal to N/2.

14. The method of claim 13 , wherein the performing the data wri

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seok Junyeong
• SONG Younggul
• Oh Eunchu
• Jang Byungchul
• Lim Joonsung

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• H10B53/20

  characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• G11C2211/5641

  Multilevel memory having cells with different number of storage levels · CPC title