Modular quantum processor architectures

Patent metadata

Field	Value
Publication number	US-12033032-B2
Application number	US-202017119089-A
Country	US
Kind code	B2
Filing date	Dec 11, 2020
Priority date	Jun 14, 2018
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

In a general aspect, a quantum processor has a modular architecture. In some aspects, a modular quantum processor includes first and second quantum processor chips and a cap structure. The first quantum processor chip is supported on a substrate layer and includes a first plurality of qubit devices. The second quantum processor chip is supported on the substrate layer and includes a second plurality of qubit devices. The cap structure is supported on the first and second quantum processor chips and includes a coupler device that provides coupling between at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices. In some instances, the coupler device is an active coupler device that is configured to selectively couple at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices.

First claim

What is claimed is:

1. A modular quantum processor comprising:
a first quantum processor chip supported on a substrate layer and comprising a first plurality of qubit devices;
a second quantum processor chip supported on the substrate layer and comprising a second plurality of qubit devices; and
a cap structure supported on the first and second quantum processor chips and comprising an active coupler device, wherein the active coupler device is configured to selectively couple at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices.

2. The modular quantum processor of claim 1 , wherein the substrate layer comprises one of:
a substrate, and the first and second quantum processor chips are supported on the substrate; or
a printed circuit board, and the first and second quantum processor chips are each bonded to the printed circuit board.

3. The modular quantum processor of claim 2 , wherein the substrate layer comprises:
signal lines configured to communicate signals between the first plurality of qubit devices and an external control system; and
signal lines configured to communicate signals between the second plurality of qubit devices and the external control system.

4. The modular quantum processor of claim 2 , comprising:
a two-dimensional array of quantum processor chips supported on the substrate layer, each quantum processor chip comprising a respective plurality of qubit devices; and
a plurality of cap structures supported on the two-dimensional array of quantum processor chips, each cap structure comprising signal lines configured to provide coupling between qubit devices of distinct quantum processor chips.

5. The modular quantum processor of claim 4 , wherein each of the cap structures is supported by, and provides coupling between qubit devices of, a respective subset of the quantum processor chips, each respective subset of the quantum processor chips comprising two, three or four of the quantum processor chips.

6. The modular quantum processor of claim 1 , wherein the cap structure is bonded to the first and second quantum processor chips.

7. The modular quantum processor of claim 1 , wherein the cap structure comprises:
bonds that connect the cap structure to the respective first and second quantum processor chips; and
traces that connect the active coupler device to the respective bonds.

8. The modular quantum processor of claim 1 , comprising at least one of:
a galvanic connection between the first plurality of qubit devices and the active coupler device; and a galvanic connection between the second plurality of qubit devices and the active coupler device;
a capacitive connection between the first plurality of qubit devices and the active coupler device, and a capacitive connection between the second plurality of qubit devices and the active coupler device; or
an inductive connection between the first plurality of qubit devices and the active coupler device, and an inductive connection between the second plurality of qubit devices and the active coupler device.

Assignees

• Rigetti & Co Llc

Inventors

• Scheer Michael Justin Gerchick
• Block Maxwell Benjamin
• Bloom Benjamin Jacob
• Reagor Matthew J
• Papageorge Alexander
• Yadav Kamal
• Alidoust Nasser
• Ryan Colm Andrew
• Caldwell Shane Arthur
• Mohan Yuvraj
• Polloreno Anthony
• Macaulay John Morrison
• Johnson Blake Robert

Classifications

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• G06N10/40 Primary

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

• G06F30/373

  Design optimisation · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/3947

  global · CPC title