Package comprising substrate with coupling element for integrated devices

Patent metadata

Field	Value
Publication number	US-12027476-B2
Application number	US-202217575492-A
Country	US
Kind code	B2
Filing date	Jan 13, 2022
Priority date	Jan 13, 2022
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

A package comprising a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes a dielectric layer and a plurality of interconnects. The plurality of interconnects includes a first plurality of interconnects configured as a first inductor and a second plurality of interconnects configured as a second inductor. The first integrated device is configured to be coupled to the first inductor. The second integrated device is configured to be coupled to the second inductor. The second integrated device is configured to tune the first inductor through the second inductor.

First claim

The invention claimed is:

1. A package comprising:
a substrate comprising a dielectric layer and a plurality of interconnects, wherein the plurality of interconnects comprises:
a first plurality of interconnects configured as a first inductor; and
a second plurality of interconnects configured as a second inductor;

a first die coupled to a first surface of the substrate, wherein the first integrated device is configured to be coupled to the first inductor; and
a second die coupled to a second surface of the substrate,
wherein the second die is configured to be coupled to the second inductor, and
wherein the second die is configured to tune the first inductor through the second inductor.

2. The package of claim 1 , wherein the first inductor and the second inductor are configured as a coupling element between the first die and the second die.

3. The package of claim 1 , wherein at least one winding of the first inductor overlaps vertically with at least one winding of the second inductor.

4. The package of claim 1 , wherein the first die overlaps vertically with the second die.

5. The package of claim 1 , wherein the first integrate device does not overlap vertically with the second die.

6. The package of claim 1 , further comprising a third die coupled to the first surface of the substrate,
wherein the plurality of interconnects comprises a third plurality of interconnects configured as a third inductor,
wherein the third die is configured to be coupled to the third inductor,
wherein the plurality of interconnects comprises a fourth plurality of interconnects configured as a fourth inductor,
wherein the second die is configured to be coupled to the fourth inductor, and
wherein the second die is configured to tune the third inductor through the fourth inductor.

7. The package of claim 6 , wherein the second die includes a controller die configured to tune the first inductor for the first die and/or the third inductor for the third die, based on sub-bands data and/or input bandwidth for the first die and/or the third die.

8. The package of claim 1 , further comprising:
a third die coupled to the first surface of the substrate; and
a fourth die coupled to the second surface of the substrate,
wherein the plurality of interconnects comprises a third plurality of interconnects configured as a third inductor,
wherein the third die is configured to be coupled to the third inductor,
wherein the plurality of interconnects comprises a fourth plurality of interconnects configured as a fourth inductor,
wherein the fourth die is configured to be coupled to the fourth inductor, and
wherein the fourth die is configured to tune the third inductor through the fourth inductor.

9. The package of claim 8 ,
wherein the second die includes a first controller die configured to tune the first inductor for the first die, based on sub-bands data and/or input bandwidth for the first die, and
wherein the fourth die includes a second controller die configured to tune the third inductor for the third die, based on sub-bands data and/or input bandwidth for the third die.

10. The package of claim 1 ,
wherein the first inductor includes one or more first windings, and
wherein the second inductor includes one or more second windings.

Assignees

• Qualcomm Inc

Inventors

• Suraj Prakash Fnu
• Thadesar Paragkumar Ajaybhai
• Lee John Jong-Hoon
• Raman Nikhil
• Song Peng
• Carrara Francesco

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W44/501 Primary

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10D1/20

  Inductors · CPC title

• H01F2027/2809

  on stacked layers · CPC title

• H05K1/165

  incorporating printed inductors · CPC title