Signal skew in source-synchronous system

Patent metadata

Field	Value
Publication number	US-12027197-B2
Application number	US-201917309770-A
Country	US
Kind code	B2
Filing date	Dec 11, 2019
Priority date	Dec 21, 2018
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and transmit a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.

First claim

What is claimed is:

1. A memory controller integrated circuit comprising:
a clock signal generator circuit, the clock signal generator circuit configured to generate a plurality of strobe signals, wherein each strobe signal of the plurality of strobe signals comprises a differential pair of clock signals; and
a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to:
transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal; and
transmit a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.

2. The memory controller integrated circuit of claim 1 , further comprising:
a calibration circuit configured to calibrate a first offset amount during a calibration operation, wherein the first offset amount is based on a first amount of interference attributable to transitions in the first subset of the plurality of data signals propagating on first signal lines.

3. The memory controller integrated circuit of claim 2 , further comprising:
a delay circuit configured to skew the first strobe signal of the plurality of strobe signals by the first offset amount, the delay circuit comprising an associated register to store a first value representing the first offset amount.

4. The memory controller integrated circuit of claim 3 , wherein the delay circuit is further configured to:
skew the second strobe signal of the plurality of strobe signals by a second offset amount with respect to the first strobe signal when transmitting the second subset of the plurality of data signals to the memory module.

5. The memory controller integrated circuit of claim 1 , wherein the memory controller integrated circuit comprises a dynamic random access memory (DRAM) controller.

6. The memory controller integrated circuit of claim 1 , wherein the memory interface circuit is further configured to:
transmit a first clock signal to the memory module; and
transmit a plurality of command/address signals to the memory module, the plurality of command/address signals to convey a memory access command and an address, wherein the plurality of command/address signals are phase aligned with the first clock signal.

7. A method of operation of a memory controller, the method comprising:
transmitting a plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and wherein each strobe signal of the plurality of strobe signals comprises a differential pair of clock signals; and
transmitting a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.

8. The method of claim 7 , further comprising:
calibrating a first offset amount during a calibration operation, wherein the first offset amount is based on a first amount of interference attributable to transitions in the first subset of the plurality of data signals propagating on first signal lines.

9. The method of claim 8 , further comprising:
programing a register of a delay circuit in the memory controller with a first value representing the first offset amount to skew the first strobe signal of the plurality of strobe signals by the first offset amount.

10. The method of claim 9 , further comprising:
programming the register of the delay circuit with a second value representing a second offset amount to skew the second strobe signal of the plurality of strobe signals by the second offset amount with respect to the first strobe signal.

11. The method of claim 7 , wherein the memory controller comprises a dynamic random access memory (DRAM) controller.

12. The method of claim 7 , further comprising:
transmitting a first clock signal to the memory module; and
transmitting a plurality of command/address signals to the memory module, the plurality of command/address signals to convey a memory access command and an address, wherein the plurality of command/address signals are phase aligned with the first clock signal.

13. A memory controller integrated circuit comprising:
a clock signal generator circuit, the clock signal generator circuit configured to generate a first plurality of signals, wherein each signal of the first plurality of signals comprises a differential pair of clock signals; and
a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to:
transmit the first plurality of signals to a memory module, wherein each of the plurality of signals is offset with respect to an adjacent signal; and
transmit a second plurality of signals to the memory module, wherein a first subset of the second plurality of signals represents a first data portion and is phase aligned with a first signal of the first plurality of signals, and wherein a second subset of the second plurality of signals represents a second data portion and is phase aligned with a second signal of the first plurality of signals.

14. The memory controller integrated circuit of claim 13 , further comprising:
a calibration circuit configured to calibrate a first offset amount during a calibration operation, wherein the first offset amount is based on a first amount of interference attributable to transitions in the first subset of the second plurality of signals propagating on first signal lines.

15. The memory controller integrated circuit of claim 14 , further comprising:
a delay circuit configured to skew the first signal of the first plurality of signals by the first offset amount, the delay circuit comprising an associated register to store a first value representing the first offset amount.

16. The memory controller integrated circuit of claim 15 , wherein the delay circuit is further configured to:
skew the second signal of the first plurality of signals by a second offset amount with respect to the first signal when transmitting the second subset of the second plurality of signals to the memory module.

17. The memory controller integrated circuit of claim 13 , wherein the memory controller integrated circuit comprises a dynamic random access memory (DRAM) controller.

18. The memory controller integrated circuit of claim 13 , wherein the memory interface circuit is further configured to:
transmit a clock signal to the memory module; and
transmit a plurality of command/address signals to the memory module, the plurality of command/address signals to convey a memory access command and an address, wherein the plurality of command/address signals are phase aligned with the clock signal.

Assignees

• Rambus Inc

Inventors

• Nikoukary Shahram
• Cho Jonghyun
• Jai Anand
• Batra Pradeep
• Luo Lei

Classifications

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title