Variable width memory module supporting enhanced error detection and correction

Patent metadata

Field	Value
Publication number	US-11705187-B2
Application number	US-202117501311-A
Country	US
Kind code	B2
Filing date	Oct 14, 2021
Priority date	Oct 8, 2015
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

First claim

What is claimed is:

1. A memory module comprising:
a primary data link, a first secondary data link, and a second secondary data link;
a first memory component coupled to the first secondary data link; and
a second memory component coupled to the second secondary data link;
the memory module operable in:
a first mode in which the memory module, responsive to successive first and second read commands to the first memory component and the second memory component, respectively, successively conveys over the primary data link first read data from the first memory component via the first secondary data link and second read data from the second memory component via the second secondary data link; and
a second mode in which the memory module, responsive to the successive first and second read commands to the first memory component and the second memory component, respectively, interleaves over the primary data link the first read data from the first memory component via the first secondary data link and the second read data from the second memory component via the second secondary data link.

2. The memory module of claim 1 , wherein the memory module operates the primary data link, the first secondary data link, and the second secondary data link at a bit rate in at least the first mode.

3. The memory module of claim 2 , wherein the memory module operates the primary data link at the bit rate in the first mode and at a second bit rate faster than the bit rate in the second mode.

4. The memory module of claim 1 , the memory module including a data-buffer component between the primary data link and each of the first and second secondary data links.

5. The memory module of claim 4 , further comprising an address-buffer component to issue the first and second read commands to the respective first and second memory components.

6. The memory module of claim 5 , the address-buffer component coupled to the data-buffer component to select between the first mode and the second mode.

7. The memory module of claim 6 , further comprising a mode register to store a value indicative of one of the first mode and the second mode.

8. The memory module of claim 1 , wherein the first memory component and the second memory component are dynamic random-access memory components.

9. A memory module comprising:
a module command link to receive module commands; and
memory slices coupled to the primary data link, each memory slice including:
first, second, third, and fourth memory components;
first, second, third, and fourth memory-component links of a memory-component width and respectively coupled to the first, second, third, and fourth memory components;
first and second primary data links, each of the memory-component width, to communicate module data responsive to the module commands; and
multiplexing logic to convey data from successive pairs of the first, second, third, and fourth memory components responsive to one of the module commands.

10. The memory module of claim 9 , the memory module supporting an access mode communicating second data from only two of the first, second, third, and fourth memory components responsive to a second one of the module commands.

11. The memory module of claim 10 , further comprising a mode register to store a value indicative of the access mode.

12. The memory module of claim 9 , the memory module including an address-buffer component coupled to a data-buffer component.

13. The memory module of claim 9 , wherein the primary data link communicates at a first bit rate and the memory-component links communicate at a second bit rate lower than the first bit rate.

14. The memory module of claim 9 , further comprising an address-buffer component and a plurality of data-buffer components, the address-buffer component to issue secondary commands to the data-buffer components responsive to the module commands.

15. A method comprising:
receiving a primary read command;
deriving, from the primary read command, secondary read commands and at least one buffer command;
sending a first of the secondary read commands to a first memory component and a second of the secondary read commands to a second memory component, the first memory component issuing first read data responsive to the first secondary read command and the second memory component issuing second read data responsive to the second secondary read command; and
sending the at least one buffer command to a data-buffer component coupled to the first memory component and the second memory component, the data-buffer component interleaving the first read data with the second read data responsive to the at least one buffer command.

16. The method of claim 15 , wherein the first memory component issue the first read data at a first bit rate, the method further comprising transmitting the interleaved first and second read data at a second bit rate different from the first bit rate.

17. The method of claim 15 , wherein the first memory component issues the first read data at a bit rate, the method further comprising transmitting the interleaved first and second read data at the bit rate.

18. The method of claim 17 , wherein the first memory component and the second memory component comprise dynamic random-access memory.

19. The method of claim 15 , further comprising, before receiving the primary read command, reading a mode-register value indicative of the interleaving.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Linstadt John Eric
• Wright Kenneth L

Classifications

• G11C11/4093 Primary

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title