Memory module with local synchronization and method of operation

Patent metadata

Field	Value
Publication number	US-11513955-B2
Application number	US-202117141978-A
Country	US
Kind code	B2
Filing date	Jan 5, 2021
Priority date	Jul 27, 2013
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A memory module is operable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals and a system clock from the memory controller and to output a module clock, module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in one or more ranks, while the data buffer control signals, together with the module clock, are provided to a plurality of buffer circuits corresponding to respective groups of memory devices and are used to control data paths in the buffer circuits. The plurality of buffer circuits include clock regeneration circuits to regenerate clock signals with programmable delays from the module clock. The regenerated clock signals are provided to respective groups of memory devices so as to locally sync the buffer circuits with respective groups of memory devices.

First claim

We claim:

1. A memory module operable in a computer system having a memory controller and a system bus, the system bus including one or more clock signal lines, a set of address/control (C/A) signal lines and a plurality of sets of data/strobe signal lines, the memory module comprising:
a module control circuit configurable to receive from the memory controller a system clock via the one or more clock signal lines and input address and control (C/A) signals via the set of C/A signal lines, and to output a module clock signal and module C/A signals in response to the system clock and the input C/A signals;
memory devices organized in one or more ranks; and
buffer circuits configurable to receive the module clock signal from the module control circuit and to generate a plurality of local clock signals, wherein a respective local clock signal of the plurality of local clock signals is output by a respective buffer circuit to a respective group of the memory devices, the respective group of the memory devices including at least one respective memory device in each of the one or more ranks, the respective local clock signal having a respective programmable phase relationship with the module clock signal, the buffer circuits including logic and configuration registers, wherein respective configuration registers included in the respective buffer circuit are programmable by the logic to control the respective programmable phase relationship; and
wherein:
the memory module is operable in at least a normal operation mode and a configuration mode;
the memory module in the normal operation mode is configurable to output or receive data/strobe signals via the data/strobe signal lines in response to a memory read or write command received via the C/A signal lines;
the memory module in the configuration mode is configurable to perform a set of operations including at least one write operation to write a set of data into a set of memory locations in the memory devices and at least one read operation to read from the set of memory locations; and
the logic is further configurable to program the respective configuration registers based on information derived from the set of operations.

2. The memory module of claim 1 , wherein the respective group of the memory devices is configurable to receive the module C/A signals and the respective local clock signal from the module control circuit, and to communicate respective data and data strobe signals with the memory controller in response to the module C/A signals and the respective local clock signal via a respective set of the plurality of sets of data/strobe signal lines.

3. The memory module of claim 2 , wherein the respective buffer circuit is configurable to generate the respective local clock signal based on values stored at the respective configuration registers.

4. The memory module of claim 3 , wherein the module clock signal received at a first buffer circuit is phase shifted from the module clock signal received at a second buffer circuit closer to the module control circuit than the first buffer circuit, and wherein values stored at first configuration registers in the first buffer circuit of the buffer circuits are different from values stored at second configuration registers at the second buffer circuit of the buffer circuits.

5. The memory module of claim 1 , wherein the respective configuration registers are programmed during one or more mode register write operations.

6. The memory module of claim 5 , wherein the logic is configured to program the respective configuration registers according to signals output from the module control circuit when the memory module is in the configuration mode.

7. The memory module of claim 6 , wherein the signals output from the module control circuit are output in response to mode register command signals received from the memory controller.

8. The memory module of claim 1 , wherein the respective buffer circuit further includes a respective phase-locked loop circuit (PLL) to provide phase locking between the module clock signal and the respective local clock signal, a respective programmable delay circuit to add a respective delay to the respective local clock signal, and a respective clock driver to drive the respective local clock signal to the respective group of the memory devices.

9. The memory module of claim 8 , wherein the respective programmable delay circuit is controlled by the logic through the respective configuration registers.

10. The memory module of claim 1 , further comprising a printed circuit board, wherein the module control circuit, the buffer circuits and the memory devices are mounted on the printed circuit board, the printed circuit board including connectors formed along an edge thereof for connecting to respective ones of the one or more clock signal lines, the set of C/A signal lines and the plurality of sets of data/strobe signal lines, and wherein the buffer circuits are distributed along the edge of the printed circuit board and between the memory devices and the edge connectors.

11. A method of operating a memory module coupled to a memory controller via a system bus, the system bus including one or more clock signal lines, a set of address/control (C/A) signal lines and a plurality of sets of data/strobe signal lines, the memory module including memory devices organized in one or more ranks, the method comprising:
receiving a system clock from the memory controller via the one or more clock signal lines and input address and control (C/A) signals from the memory controller via the set of C/A signal lines;
outputting a module clock signal and module C/A signals in response to the system clock and the input C/A signals;
generating a plurality of local clock signals in response to the module clock signal; and
outputting a respective local clock signal of the plurality of local clock signals to a respective group of the memory devices, the respective group of the memory devices including at least one memory device in each of the one or more ranks, the respective local clock signal having a respective programmable phase relationship with the module clock signal;
wherein the memory module is operable in at least a normal operation mode and a configuration mode, the method further comprising
outputting or receiving data/strobe signals via the data/strobe signal lines in response to a memory read or write command received via the C/A signal lines when the memory module is in the normal operation mode;
performing a set of operations including at least one write operation to write a set of data into a set of memory locations in the memory devices and at least one read operation to read from the set of memory locations when the memory module is in the configuration mode; and
programming the respective programmable phase relationship based on information derived from the set of operations when the memory module is in the configuration mode;
wherein the memory module further comprises:
a module control circuit configurable to receiving the system clock from the memory controller via the one or more clock signal lines and the input address and control (C/A) signals from the memory controller via the set of C/A signal lines, and to output the module clock signal and the module C/A signals in response to the system clock and the input C/A signals;
a plurality of buffer circuits configurable to receive the module clock signal from the module control circuit and to generate the plurality of local clock signals, wherein each respective buffer circuit of the plurality of buffer circuits is coupled to a respective group of the memory devices and is configurable to output the respective local clock sig

Assignees

• Netlist Inc

Inventors

• Lee Hyun
• Bhakta Jayesh R

Classifications

• G11C7/1066

  Output synchronization · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title