Synchronizing systems-on-chip using GPIO timestamps

Patent metadata

Field	Value
Publication number	US-12021611-B2
Application number	US-202117496261-A
Country	US
Kind code	B2
Filing date	Oct 7, 2021
Priority date	Oct 7, 2021
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

An electronic eyewear device includes first and second systems-on-chip (SoCs) having independent time bases. The first and second SoCs are connected by a shared general purpose input/output (GPIO) connection and an inter-SoC interface. The first and second SoCs are synchronized to each other by the first SoC asserting the shared GPIO connection to the second SoC where assertion of the message to the shared GPIO connection triggers an interrupt request (IRQ) at the second SoC. The first SoC records a first timestamp for assertion of the message to the GPIO connection, and the second SoC records a second timestamp of receipt of the IRQ. The first SoC sends a message including the first timestamp to the second SoC over the inter-SoC interface. The second SoC calculates a clock offset between the first and second SoCs as a difference between the first and second timestamps.

First claim

What is claimed is:

1. A method of synchronizing first and second systems-on-chip (SoCs) of an electronic eyewear device, the first and second SoCs having independent time bases, the method comprising:
(a) the first SoC asserting a shared general purpose input/output (GPIO) connection to the second SoC, assertion of the shared GPIO connection triggering an interrupt request (IRQ) at the second SoC;
(b) the first SoC recording a first timestamp for a time of assertion of the shared GPIO connection;
(c) the second SoC recording a second timestamp of receipt of the IRQ on the shared GPIO connection;
(d) the first SoC sending a message including the first timestamp to the second SoC over an inter-SoC interface;
(e) the second SoC calculating a clock offset between the first SoC and the second SoC as a difference between the first timestamp and the second timestamp; and
(f) the second SoC calculating a clock of the first SoC as a sum of the local timestamp and the calculated clock offset.

2. The method of claim 1 , further comprising adjusting a clock of the second SoC to the calculated clock of the first SoC.

3. The method of claim 2 , further comprising repeating steps (a)-(f) periodically and adjusting the clock of the second SoC to adjust for any drift in the clock of the first SoC or the clock of the second SoC over time.

4. The method of claim 3 , further comprising extrapolating calculated clock offsets to determine when the clock of the second SoC is expected to differ outside of a clock drift tolerance and adjusting the clock of the second SoC to the calculated clock of the first SoC to keep the calculated clock offsets within the clock drift tolerance.

5. The method of claim 1 , further comprising repeating steps (a)-(f) each time the GPIO connection from the first SoC to the second SoC is asserted.

6. The method of claim 1 , wherein the first SoC sending a message including the first timestamp to the second SoC over the inter-SoC interface includes sending the message including the first timestamp using PCIe messaging.

7. The method of claim 1 , wherein at least one of the first SoC recording a first timestamp or the second SoC recording a second timestamp comprises using a hardware timestamping feature of the first SoC or the second SoC.

8. An electronic eyewear device comprising:
a first system-on-chip (SoC) comprising a first clock generator that generates a first clock signal for the first SoC;
a second SoC comprising a second clock generator that generates a second clock signal for the second SoC, the first clock generator and the second clock generator being independent of each other;
a shared general purpose input/output (GPIO) connection between the first SoC and the second SoC;
an inter-SoC interface between the first SoC and the second SoC; and
at least one computer readable medium comprising instructions stored thereon that are executable by at least one of the first SoC or the second SoC to cause the at least one of the first SoC or the second SoC to perform operations for synchronizing the first SoC and the second SoC, the operations including:
(a) the first SoC asserting the shared GPIO connection to the second SoC, assertion of the message to the shared GPIO connection triggering an interrupt request (IRQ) at the second SoC;
(b) the first SoC recording a first timestamp for a time of assertion of the shared GPIO connection;
(c) the second SoC recording a second timestamp of receipt of the IRQ on the shared GPIO connection;
(d) the first SoC sending a message including the first timestamp to the second SoC over the inter-SoC interface;
(e) the second SoC calculating a clock offset between the first SoC and the second SoC as a difference between the first timestamp and the second timestamp; and
(f) the second SoC calculating a primary clock of the first SoC as a sum of the local timestamp and the calculated clock offset.

9. The electronic eyewear device of claim 8 , wherein the at least one computer readable medium further comprises instructions stored thereon that are executable by at least one of the first SoC or the second SoC to cause the at least one of the first SoC or the second SoC to perform operations including adjusting a clock output by the second clock generator to the calculated primary clock.

10. The electronic eyewear device of claim 9 , wherein the at least one computer readable medium further comprises instructions stored thereon that are executable by at least one of the first SoC or the second SoC to cause the at least one of the first SoC or the second SoC to perform operations including repeating steps (a)-(f) periodically and adjusting the clock output by the second clock generator to adjust for any drift in the clock output by the first clock generator or in the clock output by the second clock generator over time.

11. The electronic eyewear device of claim 10 , wherein the at least one computer readable medium further comprises instructions stored thereon that are executable by at least one of the first SoC or the second SoC to cause the at least one of the first SoC or the second SoC to perform operations including extrapolating calculated clock offsets to determine when the clock of the second SoC is expected to differ outside of a clock drift tolerance and adjusting the clock of the second SoC to the calculated primary clock to keep the calculated clock offsets within the clock drift tolerance.

12. The electronic eyewear device of claim 8 , wherein the at least one computer readable medium further comprises instructions stored thereon that are executable by at least one of the first SoC or the second SoC to cause the at least one of the first SoC or the second SoC to perform operations including repeating steps (a)-(f) each time the GPIO connection from the first SoC to the second SoC is asserted.

13. The electronic eyewear device of claim 8 , wherein the at least one computer readable medium further comprises instructions stored thereon that are executable by at least one of the first SoC or the second SoC to cause the at least one of the first SoC or the second SoC to perform operations including sending the message including the first timestamp using PCIe messaging.

14. The electronic eyewear device of claim 8 , wherein at least one of the first SoC or the second SoC includes a hardware timestamping feature for recording at least one of the first timestamp or the second timestamp.

15. The electronic eyewear device of claim 8 , wherein the GPIO connection is independent of a communication channel over the inter-SoC interface.

16. At least one non-transitory computer readable medium comprising instructions stored thereon that are executable by at least one of a first system-on-chip (SoC) or a second SoC to cause the at least one of the first SoC or the second SoC to perform operations for synchronizing the first SoC and the second SoC, the operations including:
(a) the first SoC asserting a shared general purpose input/output (GPIO) connection to the second SoC, assertion of the message to the shared GPIO connection triggering an interrupt request (IRQ) at the second SoC;
(b) the first SoC recording a first timestamp for a time of assertion of the shared GPIO connection;
(c) the second SoC recording a second timestamp of receipt of the IRQ on the shared GPIO connection;
(d) the first SoC sending a message including the first timestamp to the second SoC over an inter-SoC interface;
(e) the second SoC calculating a clock offset between the first SoC and the second SoC as a difference between the first timestamp and the second timestamp;

Assignees

• Ahn Samuel
• Ryuma Dmitry
• Zhuang Richard
• Snap Inc

Inventors

• Ahn Samuel
• Ryuma Dmitry
• Zhuang Richard

Classifications

• G06F2213/0038

  System on Chip · CPC title

• G06F2213/0026

  PCI express · CPC title

• H04J3/065 Primary

  using timestamps · CPC title

• G06F13/423

  with synchronous protocol · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title