Dual-path digital-to-time converter

Patent metadata

Field	Value
Publication number	US-10320401-B2
Application number	US-201715784022-A
Country	US
Kind code	B2
Filing date	Oct 13, 2017
Priority date	Oct 13, 2017
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

An example digital-to-time converter (DTC) includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal; and a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.

First claim

What is claimed is:

1. A digital-to-time converter (DTC), comprising:
a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal, wherein each of the plurality of delay cells includes a first multiplexer and first and second delay circuits coupled to the first multiplexer; and
a dynamic element matching (DEM) controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.

2. The DTC of claim 1 , further comprising:
a phase detector coupled to an output of the delay chain circuit;
an accumulator coupled to an output of the phase detector; and
a calibration circuit coupled to an output of the accumulator and an input of the DEM controller, the calibration circuit including an input to receive a control signal.

3. The DTC of claim 1 , wherein each of the plurality of delay cells includes a first delay circuit and a second delay circuit, wherein the delay chain circuit includes a first path through the plurality of delay cells and a second path through the plurality of delay cells, and wherein each of the plurality of delay cells couples the first delay circuit thereof to the first path and the second delay circuit thereof to the second path, or the second delay circuit thereof to the first path and the first delay circuit thereof to the second path, based on a respective one of the plurality of control signals.

4. The DTC of claim 1 , wherein each of the plurality of delay cells includes a second multiplexer and first and second delay circuits coupled between the first and second multiplexers.

5. The DTC of claim 4 , wherein the first multiplexer and the second multiplexer of each of the plurality of delay cells includes a plurality of transmission gates.

6. The DTC of claim 4 , wherein the first and second delay circuits of each of the plurality of delay cells each include a first inverter, a second inverter, and a switched capacitor array coupled between the first and second inverters.

7. The DTC of claim 4 , wherein the first multiplexer and the second multiplexer of each of the plurality of delay cells includes a plurality of three-state inverters, and wherein the first and second delay circuits of each of the plurality of delay cells each include a switched capacitor array coupled between the first and second multiplexers.

8. The DTC of claim 1 , wherein the delay chain circuit includes a plurality of separate delay chains, each of the plurality of separate delay chains include a portion of the plurality of delay cells, and wherein the DEM controller includes a plurality of separate DEM controllers respectively coupled to the plurality of separate delay chains.

9. A digital phase-locked loop (DPLL), comprising:
a digitally controlled oscillator (DCO) configured to generate a clock signal; and
a digital-to-time converter (DTC) having first input coupled to an output of the DCO and a second input configured to receive a reference clock signal, the DTC including:
a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive the reference clock signal and a second input to receive the clock signal, wherein each of the plurality of delay cells includes a first multiplexer and first and second delay circuits coupled to the first multiplexer; and
a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.

10. The DPLL of claim 9 , wherein the DTC further comprises:
a phase detector coupled to an output of the delay chain circuit;
an accumulator coupled to an output of the phase detector; and
a calibration circuit coupled to an output of the accumulator and an input of the DEM controller, the calibration circuit including an input to receive a control signal.

11. The DPLL of claim 9 , wherein each of the plurality of delay cells includes a first delay circuit and a second delay circuit, wherein the delay chain circuit includes a first path through the plurality of delay cells and a second path through the plurality of delay cells, and wherein each of the plurality of delay cells couples the first delay circuit thereof to the first path and the second delay circuit thereof to the second path, or the second delay circuit thereof to the first path and the first delay circuit thereof to the second path, based on a respective one of the plurality of control signals.

12. The DPLL of claim 9 , wherein each of the plurality of delay cells includes a second multiplexer and first and second delay circuits coupled between the first and second multiplexers.

13. The DPLL of claim 12 , wherein the first multiplexer and the second multiplexer of each of the plurality of delay cells includes a plurality of transmission gates.

14. The DPLL of claim 13 , wherein the first and second delay circuits of each of the plurality of delay cells each include a first inverter, a second inverter, and a switched capacitor array coupled between the first and second inverters.

15. The DPLL of claim 12 , wherein the first multiplexer and the second multiplexer of each of the plurality of delay cells includes a plurality of three-state inverters, and wherein the first and second delay circuits of each of the plurality of delay cells each include a switched capacitor array coupled between the first and second multiplexers.

16. The DPLL of claim 9 , wherein the delay chain circuit includes a plurality of separate delay chains, each of the plurality of separate delay chains include a portion of the plurality of delay cells, and wherein the DEM controller includes a plurality of separate DEM controllers respectively coupled to the plurality of separate delay chains.

17. A method of digital-to-time conversion, comprising:
coupling a first clock signal to a first delay path and a second clock signal to a second delay path, each of the first and second delay paths implemented by a delay chain circuit having a plurality of delay cells coupled in sequence, wherein each of the plurality of delay cells includes a multiplexer and first and second delay circuits coupled to the multiplexer;
providing a plurality of control signals to the plurality of delay cells to adjust delay of the first delay path with respect to the second delay path.

18. The method of claim 17 , wherein each of the plurality of delay cells includes a first delay circuit and a second delay circuit, and wherein each of the plurality of delay cells couples the first delay circuit thereof to the first delay path and the second delay circuit thereof to the second delay path, or the second delay circuit thereof to the first delay path and the first delay circuit thereof to the second delay path, based on a respective one of the plurality of control signals.

Assignees

• Xilinx Inc

Inventors

• Ximenes Augusto R
• Verbruggen Bob W
• Erdmann Christophe

Classifications

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03K2005/00071

  by adding capacitance as a load · CPC title

• H03L7/0992

  comprising a counter or a frequency divider · CPC title

• H03L7/091 Primary

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/0994

  comprising an accumulator · CPC title