Differential current sensing circuit

Patent metadata

Field	Value
Publication number	US-12021540-B2
Application number	US-202318127400-A
Country	US
Kind code	B2
Filing date	Mar 28, 2023
Priority date	Nov 8, 2019
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

First claim

What is claimed is:

1. A differential current sensing circuit, the circuit comprising:
a capacitor operably coupled between a first signal line and a second signal line of a differential signal line and configured to produce a differential load voltage based on charging by a differential load current and a differential digital to analog converter (DAC) output current;
a comparator operably coupled to the differential signal line, wherein, when enabled, the comparator configured to generate a comparator output signal based on the differential load voltage;
a digital circuit that is operably coupled to the comparator, wherein, when enabled, the digital circuit operably coupled and configured to process the comparator output signal to generate a first digital output signal that is representative of the differential load voltage that is based on the first signal line and the second signal line of the differential signal line;
memory that stores operational instructions;
one or more processing modules operably coupled to the digital circuit and the memory, wherein, when enabled, the one or more processing modules is configured to execute the operational instructions to:
process the first digital output signal to generate a second digital output signal that is representative of the differential load voltage; and
determine a current based on at least one of the first digital output signal or the second digital output signal; and

a differential N-bit digital to analog converter (DAC) operably coupled to the one or more processing modules, wherein, when enabled, the differential N-bit DAC configured to generate the differential DAC output current based on the second digital output signal, wherein N is a positive integer, the differential DAC output current tracks the differential load current.

2. The circuit of claim 1 , wherein the second digital output signal includes a higher resolution than the first digital output signal.

3. The circuit of claim 1 , wherein:
the comparator includes a sigma-delta comparator; and
the digital circuit includes a clocked flip flop.

4. The circuit of claim 1 further comprising:
a decimation filter operably coupled to the one or more processing modules, wherein, when enabled, the decimation filter configured to process the second digital output signal to generate another digital output signal having a lower sampling rate and a higher resolution than the second digital output signal.

5. The circuit of claim 1 , wherein the first digital output signal is representative of the differential load voltage and is also based on a current flowing through a measurement resistor.

6. The circuit of claim 5 , wherein the one or more processing modules, when enabled, is further configured to determine the current based on at least one of the first digital output signal or the first digital output signal that is the current flowing through the measurement resistor.

7. The circuit of claim 5 , wherein the one or more processing modules, when enabled, is further configured to process the first digital output signal in accordance with performing band pass filtering or low pass filtering to generate the second digital output signal that is representative of the differential load voltage and is based on the current flowing through the measurement resistor.

8. The circuit of claim 5 , wherein a digital comparator includes both the comparator and the digital circuit, wherein when enabled, the digital comparator operably coupled and configured to:
receive the first signal line of the differential signal line via a first input of the digital comparator;
receive the second signal line of the differential signal line via a second input of the digital comparator; and
generate the first digital output signal that is representative of the differential load voltage and is based on the current flowing through the measurement resistor.

9. The circuit of claim 5 , wherein:
the first signal line of the differential signal line operably coupled to a first terminal of the measurement resistor via a first in-line resistor; and
the second signal line of the differential signal line operably coupled to a second terminal of the measurement resistor via a second in-line resistor.

10. The circuit of claim 9 , wherein:
a voltage source is operably coupled and configured to supply a voltage signal to the first terminal of the measurement resistor; and
a load is operably coupled to the second terminal of the measurement resistor.

11. The circuit of claim 9 further comprising:
a first current buffer operably coupled between a first input of the comparator and the first in-line resistor; and
a second current buffer operably coupled between a second input of the comparator and the second in-line resistor.

12. The circuit of claim 11 , wherein the first current buffer includes a non-unity gain, and the second current buffer includes the non-unity gain.

13. The circuit of claim 10 further comprising:
a differential current buffer operably coupled between a first input of the comparator and the first in-line resistor and also between a second input of the comparator and the second in-line resistor.

14. The circuit of claim 13 , wherein the differential current buffer includes a non-unity gain.

15. The circuit of claim 11 , wherein differential current sensing circuit is implemented as an integrated circuit.

16. A differential current sensing circuit that is implemented as an integrated circuit, the circuit comprising:
a capacitor operably coupled between a first signal line and a second signal line of a differential signal line and configured to produce a differential load voltage based on charging by a differential load current and a differential digital to analog converter (DAC) output current;
a comparator operably coupled to the differential signal line, wherein, when enabled, the comparator configured to generate a comparator output signal based on the differential load voltage;
a digital circuit that is operably coupled to the comparator, wherein, when enabled, the digital circuit operably coupled and configured to process the comparator output signal to generate a first digital output signal that is representative of the differential load voltage that is based on the first signal line and the second signal line of the differential signal line;
memory that stores operational instructions;
one or more processing modules operably coupled to the digital circuit and the memory, wherein, when enabled, the one or more processing modules is configured to execute the operational instructions to:
process the first digital output signal to generate a second digital output signal that is representative of the differential load voltage, wherein the second digital output signal includes a higher resolution than the first digital output signal; and
determine a current based on at least one of the first digital output signal or the second digital output signal; and

a differential N-bit digital to analog converter (DAC) operably coupled to the one or more processing modules, wherein, when enabled, the differential N-bit DAC configured to generate the differential DAC output current based on the second digital output signal, wherein N is a positive integer, the differential DAC output current tracks the differential load current.

17. The circuit of claim 16 , wherein the first digital output signal is representative of the differential load voltage and is also based on a current flowing through a measurement resistor that is implemented external to the integrated circuit.

Assignees

• Sigmasense Llc

Inventors

• Huynh Phuong

Classifications

• H03M3/462

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M3/476 Primary

  Non-linear conversion systems · CPC title

• H03M3/422

  having one quantiser only · CPC title

• H03M1/34

  Analogue value compared with reference values (H03M1/48 takes precedence) · CPC title

• H03M1/0854

  of quantisation noise · CPC title