Integrated circuit including standard cell and method of manufacturing the integrated circuit

Patent metadata

Field	Value
Publication number	US-12019965-B2
Application number	US-202117225773-A
Country	US
Kind code	B2
Filing date	Apr 8, 2021
Priority date	Apr 23, 2020
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

First claim

What is claimed is:

1. A method comprising:
placing a plurality of standard cells based on a standard cell library including information about a standard cell, and generating layout data; and
placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data, the filler cell being placed based on a density of a pattern formed in the standard cell,
wherein the standard cell library comprises data defining a plurality of filler cells, the plurality of filler cells comprising the first type filler cell in which an active region extending in a first direction is formed and the second type filler cell in which an active region extending in the first direction is formed, and
a density of a contact formed on the active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on the active region of the first type filler cell to contact the active region of the first type filler cell,
wherein each of the first type filler cell and the second type filler cell provide routing of signals for adjacent ones of the plurality of standard cells.

2. The method of claim 1 , wherein the placing of the filler cell comprises, when a density of a contact formed in a rule check region with the first type filler cell placed therein satisfies a density rule, maintaining the placement of the first type filler cell.

3. The method of claim 1 , wherein the placing of the filler cell comprises, when a density of the contact formed in a rule check region with the first type filler cell placed therein does not satisfy a density rule, substituting the first type filler cell with the second type filler cell.

4. The method of claim 1 , wherein the placing of the filler cell comprises:
when a density of a contact in a rule check region of a layout of an integrated circuit is greater than a reference value, placing the second type filler cell in the rule check region; and
when the density of the contact in the rule check region of the layout of the integrated circuit is equal to or less than the reference value, placing the first type filler cell in the rule check region.

5. The method of claim 1 , wherein a cell boundary defining the second type filler cell is spaced apart from the contact of the second type filler cell.

6. The method of claim 1 , wherein the density of the contact formed on the active region of the second type filler cell is 0.

7. The method of claim 1 , wherein a shape of the active region of the first type filler cell is a same shape as a shape of the active region of the second type filler cell.

8. The method of claim 1 , wherein the first type filler cell further comprises a via formed on the contact.

9. The method of claim 1 , wherein each of the plurality of standard cells is a function cell that comprises a logic element, and each of the first type filler cell and the second type filler cell only includes structures for the routing of signals.

10. A method comprising:
placing a plurality of standard cells based on a standard cell library including data defining a plurality of filler cells including a first type filler cell and a second type filler cell;
routing the plurality of standard cells to generate layout data; and
placing a filler cell selected from among the first type filler cell and the second type filler cell by using the layout data, the filler cell being placed based on a density of a pattern formed in a corresponding standard cell,
wherein each of the plurality of filler cells comprises:
a front-end layer in which a pattern configuring a transistor is formed;
a back-end layer in which a pattern providing routing to another standard cell is formed; and
a middle layer formed between the front-end layer and the back-end layer, and
a density of a middle-layer pattern of the second type filler cell is lower than a density of a middle-layer pattern of the first type filler cell,
wherein each of the first type filler cell and the second type filler cell provide routing of signals for adjacent ones of the plurality of standard cells.

11. The method of claim 10 , wherein a front-end-layer pattern of the first type filler cell is a same pattern as a front-end-layer pattern of the second type filler cell.

12. The method of claim 10 , wherein the middle-layer pattern of the first type filler cell comprises a contact contacting an active region of the transistor.

13. The method of claim 10 , wherein the placing of the filler cell comprises:
when a density of a middle-layer pattern formed in a rule check region with the first type filler cell placed therein satisfies a density rule, maintaining the placement of the first type filler cell; and
when a density of the middle-layer pattern formed in the rule check region with the first type filler cell placed therein does not satisfy the density rule, substituting the first type filler cell with the second type filler cell.

14. The method of claim 10 , wherein the placing of the filler cell comprises:
when a density of the middle-layer pattern in a rule check region of a layout of an integrated circuit is greater than a reference value, placing the second type filler cell in the rule check region; and
when a density of the middle-layer pattern in the rule check region of the layout of the integrated circuit is equal to or less than the reference value, placing the first type filler cell in the rule check region.

15. The method of claim 10 , wherein each of the plurality of standard cells is a function cell that comprises a logic element, and each of the first type filler cell and the second type filler cell only includes structures for the routing of signals.

Assignees

• Samsung Electronics Co Ltd

Inventors

• YU Jisu
• Park Jaeho
• Baek Sanghoon
• You Hyeongyu
• Lee Seungyoung
• Lim Seungman

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title