Dummy fin cell placement in an integrated circuit layout

Patent metadata

Field	Value
Publication number	US-10141296-B2
Application number	US-201715854358-A
Country	US
Kind code	B2
Filing date	Dec 26, 2017
Priority date	Jun 29, 2016
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions. A second portion of the empty region is filled with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width and comprises a second plurality of partitions.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a semiconductor device formed over a substrate;
a first plurality of dummy fin structures over a first portion of the substrate, wherein each of the first plurality of dummy fin structures has a first gate structure having a first gate width, and the first plurality of dummy fin structures being based on a first standard dummy fin cell; and
a second plurality of dummy fin structures over a second portion of the substrate, wherein each of the second plurality of dummy fin structures has a second gate structure having a second gate width different from the first gate width, and the second plurality of dummy fin structures being based on a second standard dummy fin cell,
wherein the second portion surrounds the semiconductor device and the first portion surrounds the second portion.

2. The integrated circuit of claim 1 , further comprising:
a third plurality of dummy fin structures over a third portion of the substrate,
wherein each of the third plurality of dummy fin structures has a third gate structure having a third gate width different from the first gate width and the second gate width,
the third plurality of dummy fin structures are based on a third standard dummy fin cell, and
the third portion is between the first portion and the second portion.

3. The integrated circuit of claim 2 , wherein the third portion has a higher polysilicon gate density than the first portion and the second portion.

4. The integrated circuit of claim 1 , further comprising a third plurality of dummy fin structures within the first portion of the substrate,
wherein each of the third plurality of dummy fin structures has a third gate structure having a third gate width different from the first gate width and the second gate width, and
the third plurality of dummy fin structures are based on a third standard dummy fin cell.

5. The integrated circuit of claim 1 , wherein the first and second pluralities of dummy fin structures are not utilized to form functional circuits.

6. The integrated circuit of claim 1 , wherein the first and second pluralities of dummy fin structures undergo vertical expansion by multiplying heights of the first and second standard dummy fin cells by a constant.

7. The integrated circuit of claim 1 , wherein the first and second pluralities of dummy fin structures undergo horizontal expansion by multiplying widths of the first and second standard dummy fin cells by a constant.

8. An integrated circuit, comprising:
a semiconductor device formed over a substrate;
a first plurality of dummy fin structures over a first portion of the substrate, wherein each of the first plurality of dummy fin structures has a first gate structure having a first gate width, the first plurality of dummy fin structures being based on a first standard dummy fin cell, and the first plurality of dummy fin structures comprise a first plurality of partitions; and
a second plurality of dummy fin structures over a second portion of the substrate, wherein each of the second plurality of dummy fin structures has a second gate structure having a second gate width different from the first gate width, the second plurality of dummy fin structures being based on a second standard dummy fin cell, and the second plurality of dummy fin structures comprise a second plurality of partitions,
wherein the second portion surrounds the semiconductor device and the first portion surrounds the second portion,
a quantity of the second plurality of partitions is greater than a quantity of the first plurality of partitions, and
at least one of the second plurality of dummy fin cells is larger than the second standard dummy fin cell along at least one dimension.

9. The integrated circuit of claim 8 , further comprising:
a third plurality of dummy fin structures over a third portion of the substrate, wherein each of the third plurality of dummy fin structures has a third gate structure having a third gate width different from the first gate width and the second gate width, the third plurality of dummy fin structures are based on a third standard dummy fin cell, and the third portion is between the first portion and the second portion.

10. The integrated circuit of claim 9 , wherein the third portion has a higher polysilicon gate density than the first portion and the second portion.

11. The integrated circuit of claim 8 , further comprising a third plurality of dummy fin structures within the first portion of the substrate,
wherein each of the third plurality of dummy fin structures has a third gate structure having a third gate width different from the first gate width and the second gate width,
the third plurality of dummy fin structures are based on a third standard dummy fin cell.

12. The integrated circuit of claim 8 , wherein the first and second pluralities of dummy fin structures are not utilized to form functional circuits.

13. The integrated circuit of claim 8 , wherein the first and second pluralities of dummy fin structures undergo vertical expansion by multiplying heights of the first and second standard dummy fin cells by a constant.

14. The integrated circuit of claim 8 , wherein the first and second pluralities of dummy fin structures undergo horizontal expansion by multiplying widths of the first and second standard dummy fin cells by a constant.

15. An integrated circuit, comprising:
a semiconductor device formed over a substrate;
a first plurality of dummy fin structures over a first portion of the substrate, wherein each of the first plurality of dummy fin structures has a first gate structure having a first gate width, the first plurality of dummy fin structures being based on a first standard dummy fin cell; and
a second plurality of dummy fin structures over a second portion of the substrate, wherein each of the second plurality of dummy fin structures has a second gate structure having a second gate width smaller than the first gate width, the second plurality of dummy fin structures being based on a second standard dummy fin cell,
wherein the second portion has a polysilicon gate density higher than the first portion, the second portion surrounds the semiconductor device and the first portion surrounds the second portion.

16. The integrated circuit of claim 15 , further comprising:
a third plurality of dummy fin structures over a third portion of the substrate,
wherein each of the third plurality of dummy fin structures has a third gate structure having a third gate width different from the first gate width and the second gate width,
the third plurality of dummy fin structures are based on a third standard dummy fin cell, and
the third portion is between the first portion and the second portion.

17. The integrated circuit of claim 16 , wherein the third portion has a higher polysilicon gate density than the first portion and the second portion.

18. The integrated circuit of claim 15 , further comprising a third plurality of dummy fin structures within the first portion of the substrate,
wherein each of the third plurality of dummy fin structures has a third gate structure having a third gate width different from the first gate width and the second gate width,
the third plurality of dummy fin structures are based on a third standard dummy fin cell.

19. The integrated circuit of claim 15 , wherein the first and second pluralities of dummy fin structures undergo vertical expansion by multiplying heights of the first and second standard dummy fin cells by a constant.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsieh Tung-Heng
• Lee Tzung-Chi
• Chang Yu-Jung
• Young Bao-Ru

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2117/06

  Spare resources, e.g. for permanent fault suppression · CPC title

• H01L29/6681

  Electricity · mapped topic

• H01L27/0207 Primary

  Electricity · mapped topic

• G06F17/5072

  Physics · mapped topic