Semiconductor device with reduced leakage current

Patent metadata

Field	Value
Publication number	US-10050028-B2
Application number	US-201715475257-A
Country	US
Kind code	B2
Filing date	Mar 31, 2017
Priority date	Nov 28, 2016
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

An integrated circuit includes a substrate and a first set of functional cell units formed over the substrate. Each of the functional cell units includes a pair of functional cells that have different threshold voltages and a filler cell between the functional cells thereof. A number of the functional cell units in the first set is equal to or greater than a number of a second set of functional cell units, each of which includes a pair of functional cells that have different threshold voltages and that abut against each other. As such, a leakage current of the integrated circuit is reduced.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate; and
a first set of functional cell units formed over the substrate, each of the functional cell units comprising:
a first pair of functional cells, a first cell in the first pair having a first threshold voltage and a second cell in the first pair having a second threshold voltage; and
a filler cell between the functional cells thereof;

a second set of functional cell units, each of which includes a second pair of functional cells, a third cell in the pair having a third threshold voltage and a fourth cell in the second pair having a fourth threshold voltage, the third cell and the fourth cell abutting against each other;
wherein a first number of the functional cell units in the first set is equal to or greater than a second number of the functional cell units in the second set.

2. The integrated circuit of claim 1 , wherein a ratio of the first number to the sum of the first and second numbers ranges from 0.5 to 1.

3. The integrated circuit of claim 1 , wherein the filler cell of one of the functional cell units in the first set has a filler gate electrode.

4. The integrated circuit of claim 3 , wherein the filler gate electrode is floating.

5. The integrated circuit of claim 3 , wherein the filler gate electrode is tied to a power supply line.

6. The integrated circuit of claim 1 , wherein the filler cell of one of the functional cell units in first set has no filler gate electrode.

7. The integrated circuit of claim 1 , wherein one of the functional cell units in the first set further includes a second filler cell between the functional cells thereof.

8. The integrated circuit of claim 1 , further comprising:
an active gate electrode;
a first dummy gate electrode; and
a second dummy gate electrode, wherein the ratio of a distance between the first and second dummy gate electrodes to a pitch of the active gate electrode and the first dummy gate electrode is about 2.

9. The integrated circuit of claim 1 , further comprising:
an active gate electrode;
a first dummy gate electrode; and
a second dummy gate electrode, wherein the ratio of a distance between the first and second dummy gate electrodes to a pitch of the active gate electrode and the first dummy gate electrode is about 1.

10. A semiconductor device, the device comprising:
a substrate;
a first set of pairs of continuous active regions, each of which comprises opposite first and second end portions and an intermediate portion between the opposite first and second end portions thereof;
a filler cell that spans between each of the intermediate portions of each of the continuous active regions in each pair in the first set;
a second set of pairs of continuous active regions, each of which includes first and second end portions that abut against each other;
wherein each of the continuous active regions in the first and second sets is doped such that the first and second end portions thereof have different dopant concentrations; and
wherein a first number of the continuous active regions in the first set is equal to or greater than a second number of continuous active regions in the second set.

11. The device of claim 10 , further comprising:
a first functional cell that spans between each of the opposite first end portions of each of the continuous active regions in each pair in the first set;
a second functional cell that spans between each of the opposite second end portions of each of the continuous active regions in each pair in the first set;
a third functional cell that spans between each of the first end portions of each of the continuous active regions in each pair in the second set; and
a fourth functional cell that spans between each of the second end portions of each of the continuous active regions in each pair in the second set.

12. The device of claim 10 , wherein the filler cell has a filler gate electrode.

13. The device of claim 10 , wherein the filler cell does not have a filler gate electrode.

14. The device of claim 10 , wherein the filler cell includes a first filler cell that has a filler gate electrode and a second filler cell that does not have a filler gate electrode.

15. The device of claim 10 , wherein a ratio of the first number to the sum of the first and second numbers ranges from 0.5 to 1.

16. A semiconductor device, comprising:
a substrate that has a first set of continuous active regions, each of which has opposite first and second end portions and an intermediate portion between the opposite first and second end portions thereof;
a filler cell in the intermediate portion of each of the continuous active regions in the first set;
a first functional cell in the first end portion of each of the continuous active regions in the first and second sets, the first functional cell operating at a first threshold voltage; and
a second functional cell in the second end portion of each of the continuous active regions in the first and second sets that has a work function different from a work function of the first functional cell, the second functional cell operating at a second threshold voltage that is different from the first threshold voltage;
a second set of continuous active regions, each of which includes first and second end portions that abut against each other; and
wherein a first number of the continuous active regions in the first set is equal to or greater than a second number of the continuous active regions in the second set.

17. The device of claim 16 , wherein the filler cell includes a filler cell that has a floating filler gate electrode.

18. The device of claim 16 , wherein the filler cell includes a filler cell that has a filler gate electrode tied to a power supply line.

19. The device of claim 16 , wherein the filler cell includes a filler cell that does not have a filler gate electrode.

20. The device of claim 16 , wherein a ratio of the first to the sum of the first and second numbers ranges from 0.5 to 1.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Shih-Wei
• Wang Chung-Hsing
• Chen Chih-Liang
• Young Charles Chew-Yuen
• Tzeng Jiann-Tyng
• Chiu Yi-Hsun
• Hou Yuan-Te

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H01L27/0207 Primary

  Electricity · mapped topic

• G06F17/5072

  Physics · mapped topic