Storage controller compressing indicator data, storage device including the same, and method of operating the same

Patent metadata

Field	Value
Publication number	US-12019871-B2
Application number	US-202217865621-A
Country	US
Kind code	B2
Filing date	Jul 15, 2022
Priority date	Dec 15, 2021
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

A method of operating a storage controller includes receiving raw data indicating a series of bits each corresponding to one of threshold voltage states, performing a first state shaping for reducing a number of first target bits of the series of bits, logical values of the first target bits being equal to a logical value of a target threshold voltage state of the threshold voltage states in a first page of plural pages, generating first indicator data that indicates the first target bits based on the first state shaping, compressing the first indicator data, and storing the compressed first indicator data.

First claim

What is claimed is:

1. A method of operating a storage controller, the method comprising:
receiving raw data indicating a series of bits each corresponding to one of a plurality of threshold voltage states;
performing a first state shaping for reducing a number of first target bits of the series of bits, logical values of the first target bits being equal to a logical value of a target threshold voltage state of the plurality of threshold voltage states in a first page of a plurality of pages;
generating first indicator data that indicates the first target bits based on the first state shaping;
performing a second state shaping for reducing a number of second target bits of the series of bits to which the first state shaping is applied, the second target bits being some of the first target bits and logical values of the second target bits being equal to a logical value of the target threshold voltage state in a second page of the plurality of pages;
generating second indicator data that indicates the second target bits, based on the second state shaping;
compressing the first indicator data using a first compression algorithm optimized for the first page;
compressing the second indicator data using a second compression algorithm optimized for the second page; and
storing the compressed first indicator data and the compressed second indicator data.

2. The method of claim 1 , further comprising:
decompressing the compressed first indicator data that is stored,
wherein the second state shaping is performed based on the decompressed first indicator data.

3. The method of claim 2 , wherein:
the first compression algorithm has a lowest error rate with regard to the first page, from among a plurality of compression algorithms, and
the second compression algorithm has a lowest error rate with regard to the second page, from among the plurality of compression algorithms.

4. The method of claim 2 , further comprising:
decompressing the compressed second indicator data that is stored;
performing a third state shaping for reducing a number of third target bits of the series of bits to which the second state shaping is applied, based on the decompressed second indicator data, the third target bits being some of the second target bits and logical values of the third target bits being equal to a logical value of the target threshold voltage state in a third page of the plurality of pages; and
storing the series of bits, to which the third state shaping is applied, in a plurality of memory cells of a non-volatile memory device as encoding data.

5. The method of claim 4 , wherein each of the plurality of memory cells is implemented with a triple level cell (TLC), and
wherein the first page, the second page, and the third page correspond to a least significant bit, a center significant bit, and a most significant bit, respectively.

6. The method of claim 2 , further comprising:
decompressing the compressed second indicator data that is stored;
performing a third state shaping for reducing a number of third target bits of the series of bits to which the second state shaping is applied, based on the decompressed second indicator data, the third target bits being some of the second target bits and logical values of the third target bits being equal to a logical value of the target threshold voltage state in a third page of the plurality of pages;
generating third indicator data that indicates the third target bits based on the third state shaping;
compressing the third indicator data;
storing the compressed third indicator data;
decompressing the compressed third indicator data that is stored;
performing a fourth state shaping for reducing a number of fourth target bits of the series of bits to which the third state shaping is applied, based on the decompressed third indicator data, the fourth target bits being some of the third target bits and logical values of the fourth target bits being equal to a logical value of the target threshold voltage state in a fourth page of the plurality of pages; and
storing the series of bits, to which the fourth state shaping is applied, in a plurality of memory cells of a non-volatile memory device as encoding data.

7. The method of claim 6 , wherein each of the plurality of memory cells is implemented with a quadruple level cell (QLC), and
wherein the first page, the second page, the third page, and the fourth page correspond to a least significant bit, a first center significant bit, a second center significant bit, and a most significant bit, respectively.

8. The method of claim 1 , wherein the first indicator data include a series of indicator bits corresponding to the series of bits to which the first state shaping is applied, and
wherein a value of each of the series of indicator bits is set to:
a first value when a corresponding bit of the series of bits to which the first state shaping is applied corresponds to the first target bits; and
a second value when the corresponding bit does not correspond to the first target bits.

9. The method of claim 1 , wherein the first indicator data include a series of indicator bits corresponding to the series of bits to which the first state shaping is applied, and
wherein the first compression algorithm applies a logical operation to arbitrary two bits of the series of indicator bits.

10. The method of claim 9 , wherein the series of indicator bits of the first indicator data are first to N-th indicator bits,
wherein the first compression algorithm includes performing the logical operation on a first indicator bit of the first to N-th indicator bits and a (1+2 M ) indicator bit of the first to N-th indicator bits, “N” being a natural number of 2 or more, and “M” being an integer that is not a negative number.

11. The method of claim 1 , wherein the target threshold voltage state is a state having a highest in voltage level from among the plurality of threshold voltage states.

12. The method of claim 1 , wherein the storage controller is configured to communicate with a vertical NAND (VNAND)-based non-volatile memory device.

13. The method of claim 1 , wherein the storing of the compressed first indicator data includes storing the first indicator data in a volatile memory device present in the storage controller.

14. The method of claim 1 , further comprising:
decompressing the compressed first indicator data that is stored;
generating encoding data by applying a VNAND state shaping (VSS) encoding to the raw data based on the decompressed first indicator data and the series of bits to which the first state shaping is applied; and
storing the encoding data in a non-volatile memory device.

15. The method of claim 14 , further comprising:
receiving a read command corresponding to the raw data;
reading the encoding data stored in the non-volatile memory device, based on the read command; and
performing a VSS decoding on the encoding data.

16. A storage controller comprising:
a shape encoder configured to receive raw data indicating a series of bits each corresponding to one of a plurality of threshold voltage states, to perform a first state shaping for reducing a number of first target bits of the series of bits for a first page of a plurality of pages, to generate first indicator data that indicates the first target bits based on the first state shaping, to perform a second state shaping for reducing a number of second target bits of the series of bits to which the first state shaping is applied for a second page of the plurality of pages, and to generate second indicator data that indic

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ra Youngsuk
• Na Hanbyeul
• NOH Kwanwoo
• Seo Mankeun
• Son Hong Rak
• Jang Jae Hun

Classifications

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• H03M7/6041

  Compression optimized for errors · CPC title

• G11C2211/563

  Multilevel memory reading aspects · CPC title

• G11C2211/562

  Multilevel memory programming aspects · CPC title