Rewritable multibit non-volatile memory with soft decode optimization

Patent metadata

Field	Value
Publication number	US-9946468-B2
Application number	US-201715459578-A
Country	US
Kind code	B2
Filing date	Mar 15, 2017
Priority date	Dec 8, 2014
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.

First claim

What is claimed is:

1. A non-volatile storage device comprising:
a non-volatile memory including a plurality of non-volatile storage elements configured to store a plurality of hard bits using a plurality of physical states;
a plurality of word lines coupled to the plurality of non-volatile storage elements, each word line is associated with a plurality of bit sets including two or more hard bit sets and one or more soft bit sets;
a controller in communication with the non-volatile memory, the controller configured to encode user data from a host device by interleaved coding across all of the hard bit sets associated with a selected word line and shape the user data over all of the physical states; and
one or more read/write circuits configured to apply time-domain sensing to determine a threshold voltage of each non-volatile storage element of the selected word line using a continuous scanning voltage in response to a read request;
wherein the controller receives in response to each read request a plurality of hard bits and one or more soft bits for each non-volatile storage element of the selected word line in a single sequence.

2. The non-volatile storage device of claim 1 , wherein the one or more read/write circuits are configured to determine the plurality of hard bits and the one or more soft bits for each non-volatile storage element using the continuous scanning voltage in response to each read request from the controller.

3. The non-volatile storage device of claim 1 , wherein:
the controller is configured to perform an initial decode of the user data based on the plurality of hard bits and the one or more soft bits associated with the selected word line.

4. The non-volatile storage device of claim 3 , wherein:
the initial decode is a hard bit decode that uses the plurality of hard bits and the one or more soft bits for each storage element; and
the controller is configured to perform one or more soft bit decodes based on the plurality of hard bits and the one or more soft bits in response to a failure of the hard bit decode.

5. The non-volatile storage device of claim 2 , wherein the one or more read/write circuits are configured to determine the plurality of hard bits and the one or more soft bits for each non-volatile storage element using the continuous scanning voltage during a program verify sequence.

6. An apparatus, comprising:
a group of non-volatile storage elements coupled to a word line; and
one or more control circuits coupled to the group and the word line, the one or more control circuits configured to:
apply to the word line a continuous scanning voltage signal that spans a range of read reference levels for a plurality of physical states;
determine a threshold voltage of each non-volatile storage element based on time-domain sensing while applying the continuous scanning voltage signal;
determine state information for each non-volatile storage element based on the threshold voltage from the time-domain sensing, wherein the state information exceeds a number of encoded bits in each non-volatile storage element;
transfer from the non-volatile memory the state information for each storage element; and
perform an initial decode to determine data for the plurality of storage elements based on the state information for each non-volatile storage element.

7. The apparatus of claim 6 , wherein:
the initial decode is a hard bit decode that uses a number of bits in the state information for each storage element that is equal to the number of encoded bits.

8. The apparatus of claim 7 , wherein the one or more control circuits are configured to perform one or more soft bit decodes based on the state information after the initial decode, the one or more soft bit decodes use a number of bits in the state information for each storage element that exceeds the number of encoded bits.

9. The apparatus of claim 6 , wherein:
the state information includes a plurality of hard bits and one or more soft bits for each non-volatile storage element;
the one or more control circuits include one or more read/write circuits configured to transfer the state information by transferring all of the hard bits for each non-volatile storage element from the memory together with the one or more soft bits for each non-volatile storage element; and
the one or more control circuits include a controller configured to receive all of the hard bits and the all of the soft bits associated with the word line in a single sequence from the non-volatile memory.

10. The apparatus of claim 9 , wherein:
the one or more control circuits are configured to compress the soft bits associated with the word line prior to transferring the soft bits.

11. The apparatus of claim 6 , wherein:
the group of non-volatile storage elements is part of a non-volatile memory array; and
the non-volatile memory array is arranged in a three dimensional structure.

Assignees

• Sandisk Technologies Llc

Inventors

• Conley Kevin Michael
• Cernea Raul-Adrian
• Sharon Eran
• Alrod Idan

Classifications

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title