Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9501354-B2
Application number	US-201514619639-A
Country	US
Kind code	B2
Filing date	Feb 11, 2015
Priority date	Mar 6, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A semiconductor memory device includes: a memory array; a data-maintaining component, maintaining data read from the memory array or maintaining data used for writing to the memory array; an external input/output terminal; an error correction component, coupling the data-maintaining component and performing error-detection or correcting the data input to the data-maintaining component or output data from the data-maintaining component; a compressing component, coupling between the external input/output terminal and the error correction component and compressing or extending data. The compressing component compresses data provided by the external input/output terminal, provides the compressed data to the error correction component, extends the data provided by the error correction component, and provides the extended data to the external input/output terminal.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a memory array;
a data-maintaining component, utilized to maintain data which is read from the memory array, or to maintain data which is written to the memory array;
an external input/output terminal;
an error-checking correction (ECC) component, coupled to the data-maintaining component, utilized to execute error detection or correction for data which is input to the data-maintaining component or for output data from the data-maintaining component; and
a compression component, coupled between the external input/output terminal and the ECC component, utilized to execute compression or extension for data, wherein the compression component compresses data which is provided by the external input/output terminal, provides the compressed data to the ECC component, extends data which is provided from the ECC component, and provides the extended data to the external input/output terminal, and the compression component compresses input data to become data which comprises a data type and a consistency number of the data type.

2. The semiconductor memory device as claimed in claim 1 , further comprising an input/output buffer arranged between the external input/output terminal and the compression component.

3. The semiconductor memory device as claimed in claim 1 , wherein the compression component compresses input data with logic.

4. The semiconductor memory device as claimed in claim 1 , wherein the compression component further comprises:
a comparator, utilized to compare input data and a data type; and
a counter, utilized to count the input data and a consistency number of the data type.

5. The semiconductor memory device as claimed in claim 4 , wherein the compression component further comprises:
a data-type generator, utilized to generate data type of N bytes; and
a determining unit, utilized to determine whether or not data type obtained from a comparing result of the comparator is consistent with last data type compared by the comparator; and
a compressing data generator, utilized to generate compressed data, wherein when the determining unit determines that it is not consistent, the compressing data generator generates a data type and a compressing data including consistency number of the data type.

6. The semiconductor memory device as claimed in claim 1 , wherein the compression component further comprises an extender utilized to extend compressed data including data type and consistency number of the data type to become original data.

7. The semiconductor memory device as claimed in claim 1 , wherein the compression component further comprises:
a counter, utilized to perform decrement operation for consistency number of compressed data; and
a determining unit, utilized to determine whether a counting value of the counter reaches a predetermined value or not, wherein the extender generates connection of the data type until the determining unit determines that the predetermined value is reached.

8. The semiconductor memory device as claimed in claim 1 , wherein the ECC component adds dummy data which is totally “0” or totally “1” for the compressed data.

9. The semiconductor memory device as claimed in claim 1 , wherein the data type has a changeable length.

10. The semiconductor memory device as claimed in claim 1 , wherein the memory array is a NAND-type memory array.

Assignees

• Winbond Electronics Corp

Inventors

• Murakami Hiroki

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C2029/0411

  Online error correction · CPC title