Victim cache that supports draining write-miss entries
US-2024264952-A1 · Aug 8, 2024 · US
US12019566B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12019566-B2 |
| Application number | US-202016938364-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 24, 2020 |
| Priority date | Jul 24, 2020 |
| Publication date | Jun 25, 2024 |
| Grant date | Jun 25, 2024 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Arbitrating atomic memory operations, including: receiving, by a media controller, a plurality of atomic memory operations; determining, by an atomics controller associated with the media controller, based on one or more arbitration rules, an ordering for issuing the plurality of atomic memory operations; and issuing the plurality of atomic memory operations to a memory module according to the ordering.
Opening claim text (preview).
What is claimed is: 1. A method of arbitrating atomic memory operations, the method comprising: issuing a plurality of atomic memory operations received by an atomics controller to a memory module responsive to ordering the plurality of atomic memory operations based on one or more arbitration rules and a history of two or more issued atomic memory operations, wherein the history of the two or more issued atomic memory operations indicates a recency of access of the memory module by a particular requestor associated with the two or more issued atomic memory operations. 2. The method of claim 1 wherein: ordering the plurality of atomic memory operations comprises determining, for each requestor associated with the plurality of atomic memory operations, a recency of access for the memory module; and the ordering is based on the recency of access for each requestor associated with the plurality of atomic memory operations. 3. The method of claim 1 wherein: ordering the plurality of atomic memory operations comprises determining, for each requestor associated with the plurality of atomic memory operations, a network distance to a media controller associated with the atomics controller; and the ordering is based on the network distance for each requestor associated with the plurality of atomic memory operation. 4. The method of claim 3 , wherein the network distance comprises a latency. 5. The method of claim 3 , wherein the network distance comprises a number of hops to the media controller. 6. The method of claim 1 , further comprising: determining that a rate of receiving atomic memory operations falls below a threshold; and issuing one or more other atomic memory operations independent of the one or more arbitration rules. 7. The method of claim 1 , further comprising providing, by a media controller associated with the atomics controller, to a fabric controller associated with a requestor of an atomic memory operation of the plurality of atomic memory operations, an indication that the atomic memory operation is complete. 8. A non-transitory computer readable media storing instructions that, when executed by a processor, are configured to: issue a plurality of atomic memory operations received by an atomics controller to a memory module responsive to ordering the plurality of atomic memory operations based on one or more arbitration rules and a history of two or more issued atomic memory operations, wherein the history of the two or more issued atomic memory operations indicates a recency of access of the memory module by a particular requestor associated with the two or more issued atomic memory operations. 9. The non-transitory computer readable media of claim 8 , wherein the history of atomic memory operations is stored in a buffer. 10. The non-transitory computer readable media of claim 9 , wherein the buffer further stores one or more of an indication of each requestor that generated the atomic memory operations, a time at which the atomic memory operation was received by a media controller associated with the atomics controller, an address corresponding to a memory module to which the atomic memory operation was issued, or an indication as to whether the atomic memory operation was successful. 11. The non-transitory computer readable media of claim 8 , wherein the ordering for issuing the plurality of atomic memory operations is determined, for each of the atomic memory operations, based on a weighted score of attributes of the atomic memory operation. 12. An apparatus for arbitrating atomic memory operations, the apparatus comprising: a media controller; and an atomics controller, wherein the media controller: receives a plurality of atomic memory operations; determines based on one or more arbitration rules and a history of two or more atomic memory operations issued by the media controller, an ordering for issuing the plurality of atomic memory operations, wherein the history of the two or more issued atomic memory operations indicates a recency of access of a memory module by a particular requestor associated with the two or more issued atomic memory operations; and issues the plurality of atomic memory operations to the memory module according to the ordering. 13. The apparatus of claim 12 wherein: determining the ordering for issuing the plurality of atomic memory operations comprises determining, for each requestor associated with the plurality of atomic memory operations, a recency of access for the memory module; and the ordering is based on the recency of access for each requestor associated with the plurality of atomic memory operations. 14. The apparatus of claim 12 wherein: determining the ordering for issuing the plurality of atomic memory operations comprises determining, for each requestor associated with the plurality of atomic memory operations, a network distance to the media controller; and the ordering is based on the network distance for each requestor associated with the plurality of atomic memory operation. 15. The apparatus of claim 14 , wherein the network distance comprises a latency. 16. The apparatus of claim 14 , wherein the network distance comprises a number of hops to the media controller. 17. The apparatus of claim 12 , wherein the media controller: determines that a rate of receiving atomic memory operations falls below a threshold; and issues one or more other atomic memory operations independent of the one or more arbitration rules. 18. The apparatus of claim 12 , wherein the media controller provides, to a fabric controller associated with a requestor of an atomic memory operation of the plurality of atomic memory operations, an indication that the atomic memory operation is complete. 19. The apparatus of claim 18 , wherein the indication that the atomic memory operation is complete is configured to cause the fabric controller to generate an interrupt for the requestor of the atomic memory operation. 20. The apparatus of claim 18 , wherein the indication that the atomic memory operation is complete is configured to cause the fabric controller to store a value in a register monitored by the requestor of the atomic memory operation. 21. The apparatus of claim 12 , wherein the history of atomic memory operations is stored in a buffer. 22. The apparatus of claim 21 , wherein the buffer further stores one or more of an indication of each requestor that generated the atomic memory operations, a time at which the atomic memory operation was received by the media controller, an address corresponding to a memory module to which the atomic memory operation was issued, or an indication as to whether the atomic memory operation was successful. 23. The apparatus of claim 12 , wherein determining the ordering for issuing the plurality of atomic memory operations comprises determining, for each of the atomic memory operations, a weighted score of attributes of the atomic memory operation.
to perform operations on memory · CPC title
Register arrangements · CPC title
by minimising distances, e.g. by selecting a route with minimum of number of hops · CPC title
Access to shared memory · CPC title
using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.